On Tue, 25 Jun 2024 at 01:56, Abhinav Kumar wrote:
>
>
>
> On 6/24/2024 3:46 PM, Dmitry Baryshkov wrote:
> > On Tue, 25 Jun 2024 at 01:39, Abhinav Kumar
> > wrote:
> >>
> >> + IGT dev
> >>
> >> On 6/22/2024 10:40 PM, Dmitry Baryshkov wrote:
> >>> With the introduction of the HDMI Connector frame
On 6/13/2024 4:17 AM, Dmitry Baryshkov wrote:
From: Bjorn Andersson
Some platforms provides a mechanism for configuring the mapping between
(one or two) DisplayPort intfs and their PHYs.
In particular SC8180X provides this functionality, without a default
configuration, resulting in no conn
On 6/24/2024 3:38 PM, Dmitry Baryshkov wrote:
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dpu_crtc_frame_event_cb() directly and gate
On 6/24/2024 3:46 PM, Dmitry Baryshkov wrote:
On Tue, 25 Jun 2024 at 01:39, Abhinav Kumar wrote:
+ IGT dev
On 6/22/2024 10:40 PM, Dmitry Baryshkov wrote:
With the introduction of the HDMI Connector framework the driver might
end up creating the max_bpc property with min = max = 8. IGT ins
On Tue, 25 Jun 2024 at 01:39, Abhinav Kumar wrote:
>
> + IGT dev
>
> On 6/22/2024 10:40 PM, Dmitry Baryshkov wrote:
> > With the introduction of the HDMI Connector framework the driver might
> > end up creating the max_bpc property with min = max = 8. IGT insists
> > that such properties carry the
+ IGT dev
On 6/22/2024 10:40 PM, Dmitry Baryshkov wrote:
With the introduction of the HDMI Connector framework the driver might
end up creating the max_bpc property with min = max = 8. IGT insists
that such properties carry the 'immutable' flag. Automatically set the
flag if the driver asks for
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc
assigned using dpu_encoder_as
On Tue, 25 Jun 2024 at 01:28, Abhinav Kumar wrote:
>
>
>
> On 6/22/2024 10:40 PM, Dmitry Baryshkov wrote:
> > On HDMI connectors which use drm_bridge_connector and DRM_BRIDGE_OP_HDMI
> > IGT chokes on the max_bpc property in several kms_properties tests due
> > to the the drm_bridge_connector fail
On 6/22/2024 10:40 PM, Dmitry Baryshkov wrote:
On HDMI connectors which use drm_bridge_connector and DRM_BRIDGE_OP_HDMI
IGT chokes on the max_bpc property in several kms_properties tests due
to the the drm_bridge_connector failing to reset HDMI-related
properties.
Call __drm_atomic_helper_con
On Mon, Jun 24, 2024 at 11:29 AM Dmitry Baryshkov
wrote:
>
> On Mon, 24 Jun 2024 at 20:59, Rob Clark wrote:
> >
> > On Thu, Jun 20, 2024 at 11:48 PM Luca Weiss
> > wrote:
> > >
> > > On Fri Jun 21, 2024 at 12:47 AM CEST, Konrad Dybcio wrote:
> > > >
> > > >
> > > > On 6/20/24 20:24, Dmitry Bary
The _dpu_format_get_plane_sizes_linear() already compares pitches of
the framebuffer with the calculated pitches. Move the check to the same
place, demoting DPU_ERROR to DPU_DEBUG to prevent user from spamming the
kernel log.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_
Move the call to dpu_format_populate_plane_sizes() to the atomic_check
step, so that any issues with the FB layout can be reported as early as
possible.
At the same time move the call to dpu_format_populate_addrs() to
dpu_plane_sspp_atomic_update(). This way the all layout management is
performed
Instead of passing width / height / pitches, pass drm_framebuffer
directly. This allows us to drop the useless check for !pitches, since
an array can not be NULL.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 73 ++---
1 file changed, 3
Check that the plane pitch doesn't overflow the maximum pitch size
allowed by the hardware.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +
The struct dpu_hw_fmt_layout defines hardware data layout (addresses,
sizes and pitches. Drop format field from this structure as it's not a
part of the data layout.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 31 +++---
drivers/gpu/dr
dpu_formats.c defines DPU_MAX_IMG_WIDTH and _HEIGHT, while
dpu_hw_catalog.h defines just MAX_IMG_WIDTH and _HEIGHT. Merge these
constants to remove duplication.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_fo
The DPU driver isn't expected to be used without an IOMMU. Thus the
aspace will be always present. Not to mention that mdp4/mdp5 drivers
call msm_framebuffer_iova() without such checks, as the whole
msm_framebuffer layer is expected to support both IOMMU and IOMMU-less
configurations.
Drop these u
Lift mode_config limits set by the DPU driver to the actual FB limits as
handled by the dpu_plane.c. Move 2*max_lm_width check where it belongs,
to the drm_crtc_helper_funcs::mode_valid() callback.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
Split dpu_format_populate_layout() into addess-related and
pitch/format-related parts.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
The commit b954fa6baaca ("drm/msm/dpu: Refactor rm iterator") removed
zero-init of the hw_ctl array, but didn't change the error condition,
that checked for hw_ctl[i] being NULL. Use indices check instead.
Fixes: b954fa6baaca ("drm/msm/dpu: Refactor rm iterator")
Signed-off-by: Dmitry Baryshkov
-
The dpu_plane_prepare_fb() already calls dpu_format_populate_layout().
Store the generated layout in the plane state and drop this call from
dpu_plane_sspp_update().
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/d
The function msm_framebuffer_iova() can not fail, it always returns a
valid address. Drop the useless checks (that were already performed at
the time) and make dpu_format_populate_addrs() return void.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 6 +--
Make _dpu_crtc_setup_lm_bounds() check that CRTC width is not
overflowing LM requirements. Rename the function accordingly.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/m
Historically CRTC resources (LMs and CTLs) were assigned in
dpu_crtc_atomic_begin(). The commit 9222cdd27e82 ("drm/msm/dpu: move hw
resource tracking to crtc state") simply moved resources to
struct dpu_crtc_state, without changing the code sequence. Later on the
commit b107603b4ad0 ("drm/msm/dpu:
The msm_kms_funcs::check_modified_format() callback is not used by the
driver. Drop it completely.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 43 -
drivers/gpu/drm/ms
If the dpu_format_populate_layout() fails, then FB is prepared, but not
cleaned up. This ends up leaking the pin_count on the GEM object and
causes a splat during DRM file closure:
msm_obj->pin_count
WARNING: CPU: 2 PID: 569 at drivers/gpu/drm/msm/msm_gem.c:121
update_lru_locked+0xc4/0xcc
[...]
C
-off-by: Dmitry Baryshkov
---
Changes in v5:
- Fix crash in the writeback code.
- Link to v4:
https://lore.kernel.org/r/20240624-dpu-mode-config-width-v4-0-1038c13da...@linaro.org
Changes in v4:
- Fix handling of the not visible planes with the FB being set, as
detected via the
On Mon, 24 Jun 2024 at 20:59, Rob Clark wrote:
>
> On Thu, Jun 20, 2024 at 11:48 PM Luca Weiss wrote:
> >
> > On Fri Jun 21, 2024 at 12:47 AM CEST, Konrad Dybcio wrote:
> > >
> > >
> > > On 6/20/24 20:24, Dmitry Baryshkov wrote:
> > > > On Thu, 20 Jun 2024 at 20:32, Rob Clark wrote:
> > > >>
> >
On Thu, Jun 20, 2024 at 11:48 PM Luca Weiss wrote:
>
> On Fri Jun 21, 2024 at 12:47 AM CEST, Konrad Dybcio wrote:
> >
> >
> > On 6/20/24 20:24, Dmitry Baryshkov wrote:
> > > On Thu, 20 Jun 2024 at 20:32, Rob Clark wrote:
> > >>
> > >> On Thu, May 30, 2024 at 2:48 AM Marc Gonzalez
> > >> wrote:
On Sun, Jun 23, 2024 at 10:02:59PM +0200, Krzysztof Kozlowski wrote:
> Changes since v1:
> 1. Add tags
> 2. New patches #3 and #4
> 3. Drop previous patch "dt-bindings: display/msm/gpu: constrain
>reg/reg-names per variant", because I need to investigate more.
Acked-by: Conor Dooley
Cheers,
On Mon, Jun 24, 2024 at 8:14 AM Will Deacon wrote:
>
> On Thu, May 23, 2024 at 10:52:21AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > Add an io-pgtable method to walk the pgtable returning the raw PTEs that
> > would be traversed for a given iova access.
> >
> > Signed-off-by: Rob Clark
On Thu, May 23, 2024 at 10:52:21AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> Add an io-pgtable method to walk the pgtable returning the raw PTEs that
> would be traversed for a given iova access.
>
> Signed-off-by: Rob Clark
> ---
> drivers/iommu/io-pgtable-arm.c | 51 +
On Mon, Jun 24, 2024 at 04:06:24PM GMT, Konrad Dybcio wrote:
>
>
> On 6/23/24 21:34, Krzysztof Kozlowski wrote:
> > Commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") re-used
> > amd,imageon compatible for the SM8150 just to enable headless mode due
> > to missing display controller n
Move the call to dpu_format_populate_plane_sizes() to the atomic_check
step, so that any issues with the FB layout can be reported as early as
possible.
At the same time move the call to dpu_format_populate_addrs() to
dpu_plane_sspp_atomic_update(). This way the all layout management is
performed
Split dpu_format_populate_layout() into addess-related and
pitch/format-related parts.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
The _dpu_format_get_plane_sizes_linear() already compares pitches of
the framebuffer with the calculated pitches. Move the check to the same
place, demoting DPU_ERROR to DPU_DEBUG to prevent user from spamming the
kernel log.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_
Instead of passing width / height / pitches, pass drm_framebuffer
directly. This allows us to drop the useless check for !pitches, since
an array can not be NULL.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 73 ++---
1 file changed, 3
The dpu_plane_prepare_fb() already calls dpu_format_populate_layout().
Store the generated layout in the plane state and drop this call from
dpu_plane_sspp_update().
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/d
Lift mode_config limits set by the DPU driver to the actual FB limits as
handled by the dpu_plane.c. Move 2*max_lm_width check where it belongs,
to the drm_crtc_helper_funcs::mode_valid() callback.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
Check that the plane pitch doesn't overflow the maximum pitch size
allowed by the hardware.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +
dpu_formats.c defines DPU_MAX_IMG_WIDTH and _HEIGHT, while
dpu_hw_catalog.h defines just MAX_IMG_WIDTH and _HEIGHT. Merge these
constants to remove duplication.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_fo
The function msm_framebuffer_iova() can not fail, it always returns a
valid address. Drop the useless checks (that were already performed at
the time) and make dpu_format_populate_addrs() return void.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 6 +--
The msm_kms_funcs::check_modified_format() callback is not used by the
driver. Drop it completely.
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 43 -
drivers/gpu/drm/ms
The struct dpu_hw_fmt_layout defines hardware data layout (addresses,
sizes and pitches. Drop format field from this structure as it's not a
part of the data layout.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 18 +
drivers/gpu/drm/msm
The DPU driver isn't expected to be used without an IOMMU. Thus the
aspace will be always present. Not to mention that mdp4/mdp5 drivers
call msm_framebuffer_iova() without such checks, as the whole
msm_framebuffer layer is expected to support both IOMMU and IOMMU-less
configurations.
Drop these u
Make _dpu_crtc_setup_lm_bounds() check that CRTC width is not
overflowing LM requirements. Rename the function accordingly.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar # sc7280
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/m
Historically CRTC resources (LMs and CTLs) were assigned in
dpu_crtc_atomic_begin(). The commit 9222cdd27e82 ("drm/msm/dpu: move hw
resource tracking to crtc state") simply moved resources to
struct dpu_crtc_state, without changing the code sequence. Later on the
commit b107603b4ad0 ("drm/msm/dpu:
The commit b954fa6baaca ("drm/msm/dpu: Refactor rm iterator") removed
zero-init of the hw_ctl array, but didn't change the error condition,
that checked for hw_ctl[i] being NULL. Use indices check instead.
Fixes: b954fa6baaca ("drm/msm/dpu: Refactor rm iterator")
Signed-off-by: Dmitry Baryshkov
-
If the dpu_format_populate_layout() fails, then FB is prepared, but not
cleaned up. This ends up leaking the pin_count on the GEM object and
causes a splat during DRM file closure:
msm_obj->pin_count
WARNING: CPU: 2 PID: 569 at drivers/gpu/drm/msm/msm_gem.c:121
update_lru_locked+0xc4/0xcc
[...]
C
Unlike other compositors X.org allocates a single framebuffer covering
the whole screen space. This is not an issue with the single screens,
but with the multi-monitor setup 5120x4096 becomes a limiting factor.
Check the hardware-bound limitations and lift the FB max size to
16383x16383.
Signed-of
On Mon, Jun 24, 2024 at 7:25 AM Rob Clark wrote:
>
> On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen
> wrote:
> >
> > Add support in drm/msm driver for the Adreno X185 gpu found in
> > Snapdragon X1 Elite chipset.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> >
> > drivers/gpu/drm/msm/adreno/
On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen wrote:
>
> Add support in drm/msm driver for the Adreno X185 gpu found in
> Snapdragon X1 Elite chipset.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
> drivers/gpu/drm/msm/adreno/a6
On 24/06/2024 16:06, Konrad Dybcio wrote:
>
>
> On 6/23/24 21:34, Krzysztof Kozlowski wrote:
>> Commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") re-used
>> amd,imageon compatible for the SM8150 just to enable headless mode due
>> to missing display controller nodes. This work-aroun
On 6/23/24 21:34, Krzysztof Kozlowski wrote:
Commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") re-used
amd,imageon compatible for the SM8150 just to enable headless mode due
to missing display controller nodes. This work-around was later
narrowed to the SM8150 MTP board in commit
On 6/23/24 13:06, Akhil P Oommen wrote:
Add the necessary dt nodes for gpu support in X1E80100.
Signed-off-by: Akhil P Oommen
---
[...]
+
+ opp-11 {
+ opp-hz = /bits/ 64 <11>;
+
On 6/23/24 13:06, Akhil P Oommen wrote:
Add support in drm/msm driver for the Adreno X185 gpu found in
Snapdragon X1 Elite chipset.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---
On 24/06/2024 08:21, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 01:11:48PM +0200, Krzysztof Kozlowski wrote:
>> On 23/06/2024 13:06, Akhil P Oommen wrote:
>>> This series adds support for the Adreno X1-85 GPU found in Qualcomm's
>>> compute series chipset, Snapdragon X1 Elite (x1e80100). In th
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