On Monday 13 August 2018 06:11 PM, Ricardo Ribalda Delgado wrote:
Hello again
On Mon, Aug 13, 2018 at 2:16 PM Archit Taneja wrote:
Are you seeing issues only for this mode in particular(1680x1050)? I'm
wondering if the issue is specific to a frequency range.
I have only tried
Hi,
On Monday 13 August 2018 02:24 PM, Ricardo Ribalda Delgado wrote:
Hi Archit
On Sun, Aug 12, 2018 at 9:47 AM Archit Taneja wrote:
Hi,
On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote:
Hello
I have a screen that via edid expects the following modeline by
default via
Hi,
On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote:
Hello
I have a screen that via edid expects the following modeline by
default via detailed mode:
Modeline "1680x1050"x60.0 146.30 1680 1784 1960 2240 1050 1053 1059
1089 +hsync -vsync
When the card is configured to that
Thanks, I'll give this a try.
The patch looks good, anyway. Rob's queued it for msm-next.
Archit
Therefore, I asked the X11 people where to fix:
https://www.spinics.net/lists/xorg/msg58969.html
Best regards
-Carsten
2018-07-24 19:33 GMT+02:00 Archit Taneja <mailto:arch...
Hi,
On Tuesday 17 July 2018 04:33 AM, Carsten Behling wrote:
modesetting X11 driver may provide negative x/y cordinates in
mdp5_crtc_cursor_move call when rotation is enabled.
Cursor buffer can overlap down to its negative width/height.
ROI has to be recalculated for negative x/y indicating us
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Abhinav Kumar
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Changes in v4:
- fixed commit message
Signed-off-by: Abhinav Kumar
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++---
1 fi
mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Reviewed-by: Archit Taneja
Changes in v3
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Rajesh Yadav
postdiv_lock spinlock was used before initialization
for 10nm pll. It causes following spin_bug:
"BUG: spinlock bad magic on CPU#0".
Initialize spinlock before its usage.
Reviewed-by: Archit Taneja
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Chandan Uddaraju
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Reviewed-by: Archit Taneja
Changes
current implementation even inactive nodes get added
resulting in creation of redundant connectors.
Reviewed-by: Archit Taneja
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 6 +-
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 10
On Saturday 16 June 2018 11:26 AM, Abhinav Kumar wrote:
Currently, DRM bridge for DPU relies on the default video
mode setting to set the encoder mode.
Add an explicit call to set the encoder mode for bridges.
Reviewed-by: Archit Taneja
Signed-off-by: Abhinav Kumar
---
drivers/gpu
Hi,
On Saturday 14 April 2018 12:55 PM, Abhinav Kumar wrote:
From: Archit Taneja
You can drop DPU from the subject. Also, you'd need to add
Theirry Reading for panel related patches, and Rob Herring
for an Ack on the DT bindings.
I think you can change the author to yourself. You'
V2:
-Removed Change-Id from the commit text tags.
-Remove extra parentheses
Changes in V3:
-None
Reviewed-by: Archit Taneja
Signed-off-by: Chandan Uddaraju
---
drivers/gpu/drm/msm/dsi/dsi.c | 3 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm
On Thursday 19 April 2018 01:15 AM, Chandan Uddaraju wrote:
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Reviewed-by: Archit Taneja
Changes in V2
Hi Abhinav,
Thanks for posting this driver. Some comments below.
On Saturday 07 April 2018 12:36 PM, Abhinav Kumar wrote:
From: Archit Taneja
Add support for truly dual DSI video mode panel
panel used in MSM reference platforms >
Signed-off-by: Archit Taneja
Signed-off-by: Abhinav Ku
On Saturday 07 April 2018 01:20 PM, Abhinav Kumar wrote:
Currently the DSI PHY timings are hard-coded for a specific panel
for the 10nm PHY.
Replace this with the auto PHY timing calculator which can calculate
the PHY timings for any panel.
Reviewed-by: Archit Taneja
Signed-off-by
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).
Reviewed-by: Archit Taneja
Changes in v2:
- None
Signed-o
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Don't leave the event != NULL once it's consumed, this is used a signal
s/used a/used as a ?
to the atomic helpers that the event will be handled by the driver.
Reviewed-by: Archit Taneja
Changes in v2:
- None
Cc: Jeykuma
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.
Reviewed-by: Archit Taneja
Changes in v2:
- None
Cc: Jeykumar Sankaran
Signed-off-by
- None
Cc: Jeykumar Sankaran
Cc: Archit Taneja
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 77 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 11 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c | 12 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe
Signed-off-by: Stefan Agner
Reviewed-by: Archit Taneja
Archit
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..d729b2b4b66d 1006
Hi,
On Tuesday 20 March 2018 01:28 AM, Sean Paul wrote:
Instead of subclassing atomic state, store driver private data in
private_obj/state. This allows us to remove the swap_state driver hook
for mdp5 and get closer to using the atomic helpers entirely.
Changes in v2:
- Use state->state in d
On Monday 12 March 2018 06:53 PM, Sibi S wrote:
From: Archit Taneja
I'm a bit uncertain about using this patch in its current state.
Some reasons below.
Add command broadcast support for DSI 6G v2.0+ controller
on SDM845
Signed-off-by: Sibi S
---
drivers/gpu/drm/msm/dsi/
On Monday 12 March 2018 06:53 PM, Sibi S wrote:
Replace version checks with the helper functions bound to
cfg_handler for DSI v2 and DSI 6G 1.x controllers
With the ops set up for DSI6G 2.x too:
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Sibi S
---
drivers/gpu/drm/msm
On Monday 12 March 2018 06:53 PM, Sibi S wrote:
Add dsi host helper function implementation for DSI v2
and DSI 6G 1.x controllers
Signed-off-by: Sibi S
---
drivers/gpu/drm/msm/dsi/dsi.h | 15 +++
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 44 +--
drivers/gpu/drm/msm/dsi/dsi_host.c |
On Friday 02 March 2018 05:57 AM, chand...@codeaurora.org wrote:
On 2018-03-01 07:53, Sean Paul wrote:
On Wed, Feb 28, 2018 at 04:44:49PM -0800, Chandan Uddaraju wrote:
Current DSI driver uses two connectors for dual DSI case even
though we only have one panel. Fix this by implementing one
co
On 12/01/2017 02:34 AM, Will Newton wrote:
The return value of this function is a pointer checked with
IS_ERR, so we should be returning an error pointer rather than
NULL when the init fails.
Reviewed-by: Archit Taneja
Signed-off-by: Will Newton
---
drivers/gpu/drm/msm/mdp/mdp5
ided and it matches the plane crtc coordinates
the user also provided.
Once everyone agrees on this we can move the clip handling into
drm_atomic_helper_check_plane_state().
For this and the msm change in patch # 15/15:
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Laurent Pinchart
Cc: Ro
crtc(crtc);
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
- uint32_t lm = mdp5_cstate->pipeline.mixer->lm;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w;
uint32_t roi_h;
I guess we could get rid of roi_w, r
On 10/20/2017 05:47 PM, Rob Clark wrote:
It's only likely to paper over bugs. Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.
Acked-by: Archit Taneja
Signed-o
On 08/03/2017 05:20 PM, Arnd Bergmann wrote:
When CONFIG_PM is disabled, we get harmless warnings about unused
functions:
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1025:12: error: 'mdp5_runtime_resume'
defined but not used [-Werror=unused-function]
static int mdp5_runtime_resume(struct device
ive instead of
crtc_state->enable when waiting for completion.
Tested-by: Archit Taneja
Signed-off-by: Maarten Lankhorst
Cc: Rob Clark
Cc: Archit Taneja
Cc: Vincent Abriou
Cc: Maarten Lankhorst
Cc: Russell King
Cc: Rob Herring
Cc: Markus Elfring
Cc: Sushmita Susheelendra
Cc: lin
= false, in which case it should never return an error.
Handle failure with BUG_ON for this reason.
Applied #2/12 and tried this out.
Tested-by: Archit Taneja
Signed-off-by: Maarten Lankhorst
Cc: Rob Clark
Cc: linux-arm-...@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Link:
http
:
Tested-by: Archit Taneja
Thanks,
Archit
Jordan Crouse (6):
drm/msm: Add a quick and dirty PIL loader
drm/msm: gpu: Use the zap shader on 5XX if we can
drm/msm: Improve the zap shader
drm/msm: Create a child device for the zap shader
drm/msm: Move zap shader firmware name to the device
k;
+ }
This check isn't needed. As of now, we don't create a fbdev device if we don't
have kms initialized.
Otherwise,
Reviewed-by: Archit Taneja
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 11/7/2016 8:18 PM, Rob Clark wrote:
On Mon, Nov 7, 2016 at 5:38 AM, Archit Taneja wrote:
On 11/05/2016 09:55 PM, Rob Clark wrote:
Split out the hardware pipe specifics from mdp5_plane. To start, the hw
pipes are statically assigned to planes, but next step is to assign the
hw pipes
etc, and calculate CRTCs based on that, and not number of layermixers. Maybe
add a couple for writeback too. This way, we get the right number of
CRTCs, and we don't rely on #LMs, since we can have 2 per crtc
in the future.
Reviewed-by: Archit Taneja
--
Qualcomm Innovation Center, Inc.
Hi,
Minor comments below. LGTM otherwise.
On 11/05/2016 09:56 PM, Rob Clark wrote:
(re)assign the hw pipes to planes based on required caps, and to handle
situations where we could not modify an in-use plane (ie. SMP block
reallocation).
This means all planes advertise the superset of formats
nit(&mdp5_kms->state_lock);
+ mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
+ if (!mdp5_kms->state) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
This would probably be better in mdp5_kms_init() since it's in
On 11/06/2016 07:45 PM, Rob Clark wrote:
On Fri, Nov 4, 2016 at 6:44 PM, Jordan Crouse wrote:
For reasons that are not entirely understood using dma_map_sg()
for nocache/write combine buffers doesn't always successfully flush
the cache after the memory is zeroed somewhere deep in the bowels
o
On 10/15/2016 6:38 PM, Rob Clark wrote:
On Sat, Oct 15, 2016 at 8:57 AM, Archit Taneja wrote:
On 10/15/2016 5:02 PM, Rob Clark wrote:
On Sat, Oct 15, 2016 at 5:39 AM, Archit Taneja
wrote:
On 10/13/2016 10:18 PM, Rob Clark wrote:
If the bottom-most layer is not fullscreen, we need
On 10/15/2016 5:02 PM, Rob Clark wrote:
On Sat, Oct 15, 2016 at 5:39 AM, Archit Taneja wrote:
On 10/13/2016 10:18 PM, Rob Clark wrote:
If the bottom-most layer is not fullscreen, we need to use the BASE
mixer stage for solid fill (ie. MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT). The
blend_setup
On 10/13/2016 10:18 PM, Rob Clark wrote:
If the bottom-most layer is not fullscreen, we need to use the BASE
mixer stage for solid fill (ie. MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT). The
blend_setup() code pretty much handled this already, we just had to
figure this out in _atomic_check() and assign
assign the stages appropriately.
The patch looks good. I couldn't test the problematic scenario since I
don't have an easy way to reproduce it, but it doesn't break regular
usage (where base layer is full screen).
Reviewed-by: Archit Taneja
Signed-off-by: Rob Clark
---
TODO
o previous prototype
for 'mdp4_plane_set_property' [-Wmissing-prototypes]
In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.
Reviewed-by: Arch
Hi,
On 06/18/2016 10:56 PM, weiyj...@163.com wrote:
From: Wei Yongjun
In case of error, the function drm_mode_duplicate() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
Thanks for the fix.
Reviewed-by: Archit Taneja
() and not suffer
from any backwards compatibility issues with drivers not following the
more rigorous init ordering.
Tested-by: Archit Taneja
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Rob Clark
Cc: David Airlie
Cc: dri-de...@lists.freedesktop.org
Cc: linux-arm-...@vger.kernel.org
Cc
us.
Works fine with msm.
Tested-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/msm/edp/edp_connector.c| 10 --
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 8
drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c |
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