Thank you for your response. This is exactly what I wanted to know. One
last question:
+While it
+is discouraged, it is possible to write your own prologue/epilogue code
+using asm and use ``C'' code in the middle.
I wouldn't remove the last sentence since IMO it's not the intent of the featu
On 17/05/2014 00:43, Maxim Kuvyrkov wrote:
On May 17, 2014, at 10:41 AM, Tobias Grosser wrote:
On 17/05/2014 00:27, Maxim Kuvyrkov wrote:
Hi Community,
The community bonding period is coming to a close, students can officially
start coding on Monday, May 19th.
In the past month the stude
On May 17, 2014, at 10:41 AM, Tobias Grosser wrote:
>
>
> On 17/05/2014 00:27, Maxim Kuvyrkov wrote:
>> Hi Community,
>>
>> The community bonding period is coming to a close, students can officially
>> start coding on Monday, May 19th.
>>
>> In the past month the student should have applied
On 17/05/2014 00:27, Maxim Kuvyrkov wrote:
Hi Community,
The community bonding period is coming to a close, students can officially
start coding on Monday, May 19th.
In the past month the student should have applied for FSF copyright assignment
and, hopefully, executed on a couple of test t
Hi Community,
The community bonding period is coming to a close, students can officially
start coding on Monday, May 19th.
In the past month the student should have applied for FSF copyright assignment
and, hopefully, executed on a couple of test tasks to get a feel for GCC
development.
The G
Hi Tobias,
> what is the difference you see between ISL AST generation and code
> generation?
By “ISL AST generation”, I mean ISL AST generation without generation
of GIMPLE code.
> What are your plans to separate the ISL AST generation? Do you foresee any
> difficulties/problems?
According to
Thank you!
--
Cheers, Roman Gareev
On 2014-05-16, 6:23 AM, Kugan wrote:
I would like to know if there is anyway we can use registers from
particular register class just as spill registers (in places where
register allocator would normally spill to stack and nothing more), when
it can be useful.
In AArch64, in some cases, compilin
Hi!
On Fri, 16 May 2014 15:47:58 +0400, Kirill Yukhin
wrote:
> To support the offloading features for Intel's Xeon Phi cards
> we need to add a foreign library (liboffload) into the gcc repository.
As written in the README, this library currently is specific to Intel
hardware (understan
On 05/12/2014 11:13 PM, David Wohlferd wrote:
> After updating gcc's docs about inline asm, I'm trying to improve
> some of the related sections. One that I feel has problems with
> clarity is __attribute__ naked.
>
> I have attached my proposed update. Comments/corrections are
> welcome.
>
> In
On Sat, 10 May 2014, Gerald Pfeifer wrote:
> Since (at least) 16:40 UTC that day my i386-unknown-freebsd10.0 builds
> fail as follows:
>
> Comparing stages 2 and 3
> warning: gcc/cc1obj-checksum.o differs
> warning: gcc/cc1-checksum.o differs
> warning: gcc/cc1plus-checksum.o differs
> B
On May 16, 2014, at 12:25 PM, Ian Bolton wrote:
>> On Fri, May 16, 2014 at 6:34 AM, Sheheryar Zahoor Qazi
>> wrote:
>>>
>>> I am trying to provide soft-fp support to a an 18-bit soft-core
>>> processor architecture at my university. But the problem is that
>>> libgcc has not been cross-compile
> On Fri, May 16, 2014 at 6:34 AM, Sheheryar Zahoor Qazi
> wrote:
> >
> > I am trying to provide soft-fp support to a an 18-bit soft-core
> > processor architecture at my university. But the problem is that
> > libgcc has not been cross-compiled for my target architecture and
> some
> > functions
> On 05/16/2014 12:05 PM, Kugan wrote:
> >
> >
> > On 16/05/14 20:40, pins...@gmail.com wrote:
> >>
> >>
> >>> On May 16, 2014, at 3:23 AM, Kugan
> wrote:
> >>>
> >>> I would like to know if there is anyway we can use registers from
> >>> particular register class just as spill registers (in place
On Fri, May 16, 2014 at 6:34 AM, Sheheryar Zahoor Qazi
wrote:
>
> I am trying to provide soft-fp support to a an 18-bit soft-core
> processor architecture at my university. But the problem is that
> libgcc has not been cross-compiled for my target architecture and some
> functions are missing so i
On Fri, May 16, 2014 at 4:47 AM, Kirill Yukhin wrote:
>
> To support the offloading features for Intel's Xeon Phi cards
> we need to add a foreign library (liboffload) into the gcc repository.
> README with build instructions is attached.
Can you explain why this library should be part of
Hi all,
I am trying to provide soft-fp support to a an 18-bit soft-core
processor architecture at my university. But the problem is that
libgcc has not been cross-compiled for my target architecture and some
functions are missing so i cannot build libgcc.I believe soft-fp is
compiled in libgcc so i
On 05/16/2014 12:05 PM, Kugan wrote:
>
>
> On 16/05/14 20:40, pins...@gmail.com wrote:
>>
>>
>>> On May 16, 2014, at 3:23 AM, Kugan
>>> wrote:
>>>
>>> I would like to know if there is anyway we can use registers from
>>> particular register class just as spill registers (in places where
>>> reg
Dear steering committee,
To support the offloading features for Intel's Xeon Phi cards
we need to add a foreign library (liboffload) into the gcc repository.
README with build instructions is attached.
I am also copy-pasting the header comment from one of the liboffload files.
The header
On 16/05/14 20:40, pins...@gmail.com wrote:
>
>
>> On May 16, 2014, at 3:23 AM, Kugan wrote:
>>
>> I would like to know if there is anyway we can use registers from
>> particular register class just as spill registers (in places where
>> register allocator would normally spill to stack and not
> On May 16, 2014, at 3:23 AM, Kugan wrote:
>
> I would like to know if there is anyway we can use registers from
> particular register class just as spill registers (in places where
> register allocator would normally spill to stack and nothing more), when
> it can be useful.
>
> In AArch64,
I would like to know if there is anyway we can use registers from
particular register class just as spill registers (in places where
register allocator would normally spill to stack and nothing more), when
it can be useful.
In AArch64, in some cases, compiling with -mgeneral-regs-only produces
bet
On 15/05/14 09:52, Ramana Radhakrishnan wrote:
On Thu, May 15, 2014 at 8:36 AM, Maxim Kuvyrkov
wrote:
On May 15, 2014, at 6:46 PM, Ramana Radhakrishnan
wrote:
I'm not claiming it's a great heuristic or anything. There's bound to
be room for improvement. But it was based on "reality" and re
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