On 01/29/2015 08:32 PM, Richard Henderson wrote:
On 01/29/2015 02:08 AM, Paul Shortis wrote:
I've ported GCC to a small 16 bit CPU that has single bit shifts. So I've
handled variable / multi-bit shifts using a mix of inline shifts and calls to
assembler support functions.
The calls to the asm
Hi Guys,
Myself was very new to dwarf debugging format and recently we migrate
GCC compiler to 4.8.3 toolchain from 4.5.2 ans using same binutils
2.23.51.
we are seeing the weird issue with .debug_loc entries and assembler
pop up with below error
/tmp/ccUj1tbg.s: Assembler messages:
/tmp/ccU
On 30 January 2015 at 16:58, James Dennett wrote:
> It's hardly just a loophole: C++ doesn't specify the order of evaluation,
> so the code is wrong (i.e., non-portable, as you've found).
>
> Arguably this is a design problem with IOStreams, given how
> tempting it can be to write code that assumes
On Thu, Jan 29, 2015 at 10:38 PM, Conrad S wrote:
>
> Which compiler is correct here - gcc or clang?
Both compilers are correct.
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64870
>
> Consider the following code:
>
> #include
>
> struct blah {
> inline double setval(unsigned int& x) const
>
Which compiler is correct here - gcc or clang?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64870
Consider the following code:
#include
struct blah {
inline double setval(unsigned int& x) const
{
x = 123;
return 456.0;
}
};
int
main(int argc, char** argv) {
blah blah_ins
Snapshot gcc-4.8-20150129 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.8-20150129/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.8 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
On 29-01-15 18:25, Jakub Jelinek wrote:
The stdarg pass can't grok too heavy optimizations, so if at all possible,
don't schedule such passes early, and if you for some reason do, avoid
optimizing in there the va_list related accesses.
This patch work for the example.
In pass_lim1, I get:
...
On 01/29/15 10:32, Richard Henderson wrote:
On 01/29/2015 02:08 AM, Paul Shortis wrote:
I've ported GCC to a small 16 bit CPU that has single bit shifts. So I've
handled variable / multi-bit shifts using a mix of inline shifts and calls to
assembler support functions.
The calls to the asm libra
On Thu, Jan 29, 2015 at 07:44:29PM +0100, Richard Biener wrote:
> On January 29, 2015 6:25:35 PM CET, Jakub Jelinek wrote:
> >On Thu, Jan 29, 2015 at 06:19:45PM +0100, Tom de Vries wrote:
> >> consider attached patch, which adds pass_lim after fre1 (a
> >simplification of
> >> my oacc kernels patc
On January 29, 2015 6:25:35 PM CET, Jakub Jelinek wrote:
>On Thu, Jan 29, 2015 at 06:19:45PM +0100, Tom de Vries wrote:
>> consider attached patch, which adds pass_lim after fre1 (a
>simplification of
>> my oacc kernels patch series).
>>
>> The included testcase lim-before-stdarg.c fails.
>>
>>
On 01/29/2015 02:08 AM, Paul Shortis wrote:
> I've ported GCC to a small 16 bit CPU that has single bit shifts. So I've
> handled variable / multi-bit shifts using a mix of inline shifts and calls to
> assembler support functions.
>
> The calls to the asm library functions clobber only one (by con
On Thu, Jan 29, 2015 at 06:19:45PM +0100, Tom de Vries wrote:
> consider attached patch, which adds pass_lim after fre1 (a simplification of
> my oacc kernels patch series).
>
> The included testcase lim-before-stdarg.c fails.
>
> The first sign of trouble is in lim-before-stdarg.c.088t.stdarg (a
Jakub,
consider attached patch, which adds pass_lim after fre1 (a simplification of my
oacc kernels patch series).
The included testcase lim-before-stdarg.c fails.
The first sign of trouble is in lim-before-stdarg.c.088t.stdarg (attached):
...
gen_rtvec: va_list escapes 0, needs to save 0 GPR
>>> On 29.01.15 at 09:20, wrote:
> On Wed, Jan 28, 2015 at 11:54 PM, Jan Beulich wrote:
>> Hello,
>>
>> in the Xen project we had (meanwhile fixed) code like this (meant to
>> be uniform between 32- and 64-bit):
>>
>> static inline int fls(unsigned int x) {
>> int ret;
>> asm("clz
I've ported GCC to a small 16 bit CPU that has single bit shifts.
So I've handled variable / multi-bit shifts using a mix of inline
shifts and calls to assembler support functions.
The calls to the asm library functions clobber only one (by
const) or two (variable) registers but of course call
Hi!
On Sat, 10 Jan 2015 20:21:46 +0100, I wrote:
> On Wed, 12 Nov 2014 15:43:06 -0500, David Malcolm wrote:
> > On Wed, 2014-11-12 at 21:30 +0100, Jakub Jelinek wrote:
> > > On Wed, Nov 12, 2014 at 03:22:21PM -0500, David Malcolm wrote:
> > > > On Wed, 2014-11-12 at 14:47 +0100, Jakub Jelinek wro
On Wed, Jan 28, 2015 at 11:54 PM, Jan Beulich wrote:
> Hello,
>
> in the Xen project we had (meanwhile fixed) code like this (meant to
> be uniform between 32- and 64-bit):
>
> static inline int fls(unsigned int x) {
> int ret;
> asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
>
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