gcc/ChangeLog:
* config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the Zve32f
extension.
---
gcc/config/riscv/vector-iterators.md | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/vector-iterators.md
Hi Carl,
on 2023/6/16 00:00, Carl Love wrote:
> GCC maintainers:
>
> Version 2, fixed various typos. Updated the change log body to say the
> instruction counts were updated. The instruction counts changed as a
> result of changing the first argument of the vec_replace_unaligned
> builtin call
I understand this patch is fixing VWF, VWF_ZVE64, VWEXTF, base on current
upstream codes.
I agree with "VWEXTF" changes.
But not "VWF" "VWF_ZVE64", since current reduction pattern has bugs on ZVE32*
and ZVE64* and we have refactored them:
I notice VWF_ZVE64
should be removed.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-19 09:29
To: 钟居哲; gcc-patches
CC: rdapp.gcc; Jeff Law; Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
Thanks Juzhe, will not send the V2 as only
VWF is defined under TARGET_MIN_VLEN >= 128.
VWEXTF: zvfh/zvfhmin depends on the Zve32f extension.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix requirement
---
gcc/config/riscv/vector-iterators.md | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> This patch adds a new 2-instructions constant synthesis pattern:
>
> - A non-negative square value that root can fit into a signed 12-bit:
> => "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax"
>
> Due to the execution cost of
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> It used to always return a constant 4, which is same as the default
> behavior, but doesn't take into account the effects of secondary
> reloads.
>
> Therefore, the implementation of this target hook is removed.
>
>
Hi Carl,
on 2023/6/16 00:00, Carl Love wrote:
> On Tue, 2023-06-13 at 11:24 +0800, Kewen.Lin wrote:
>> Hi Carl,
>>
>> on 2023/5/31 04:41, Carl Love wrote:
>>> GCC maintainers:
>>>
>>> The following patch fixes the first argument in the builtin
>>> definition
>>> and the corresponding test cases.
Hi!
David Edelsohn writes:
> This Message Is From an External Sender
> This message came from outside your organization.
>
> On Tue, May 30, 2023 at 11:00 PM Jiufu Guo wrote:
>
> Gentle ping...
>
> Jiufu Guo via Gcc-patches writes:
>
> > Gentle ping...
> >
> > Jiufu Guo via
Hi,
Richard Biener writes:
> On Fri, 16 Jun 2023, Jiufu Guo wrote:
>
>> Hi,
>>
>> The const_anchor in cse.cc supports integer constants only.
>> There is a "gcc_assert (SCALAR_INT_MODE_P (mode))" in
>> try_const_anchors.
>>
>> In the latest code, some non-integer modes are used with const
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110062
--- Comment #7 from Hongtao.liu ---
> pixel$red_60(D)(10)>, type of def: internal
> t.c:18:27: missed: no optab.
> t.c:18:27: missed: not vectorized: relevant stmt not supported: _29 =
> (unsigned char) pixel$red_78;
> t.c:18:27: note:
> -Original Message-
> From: Jan Beulich
> Sent: Friday, June 16, 2023 2:22 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kirill Yukhin ; Liu, Hongtao
>
> Subject: [PATCH v2] x86: make VPTERNLOG* usable on less than 512-bit
> operands with just AVX512F
>
> There's no reason to constrain this
> -Original Message-
> From: Jan Beulich
> Sent: Friday, June 16, 2023 2:20 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Liu, Hongtao ; Kirill Yukhin
>
> Subject: [PATCH v2] x86: correct and improve "*vec_dupv2di"
>
> The input constraint for the %vmovddup alternative was wrong, as the
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110235
--- Comment #8 from Hongtao.liu ---
Fixed for GCC 14, the bug is latent on all release branches, but would not be
exposed without rtl us/ss_truncate simplification.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110235
--- Comment #7 from CVS Commits ---
The master branch has been updated by hongtao Liu :
https://gcc.gnu.org/g:f8e02702726d4514b8ff9f5481c9c1f5d34e1787
commit r14-1917-gf8e02702726d4514b8ff9f5481c9c1f5d34e1787
Author: liuhongt
Date: Thu Jun
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110235
--- Comment #6 from CVS Commits ---
The master branch has been updated by hongtao Liu :
https://gcc.gnu.org/g:58e61a3ab1c13b6d5b07d86a30cf48a46e0345c8
commit r14-1916-g58e61a3ab1c13b6d5b07d86a30cf48a46e0345c8
Author: liuhongt
Date: Wed Jun
Thanks Juzhe, will not send the V2 as only commit log change.
Pan
From: 钟居哲
Sent: Monday, June 19, 2023 6:02 AM
To: Li, Pan2 ; gcc-patches
Cc: rdapp.gcc ; Jeff Law ; Li, Pan2
; Wang, Yanzhang ; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
Add
Hi,
This patch modifies vsx extract expander and generates mfvsrwz/stxsiwx
for all platforms when the mode is V4SI and the index of extracted element
is 1 for BE and 2 for LE. Also this patch adds a insn pattern for mfvsrwz
which can help eliminate redundant zero extend.
Bootstrapped and
Hi!
Segher Boessenkool writes:
> Hi!
>
> On Fri, Jun 16, 2023 at 04:34:12PM +0800, Jiufu Guo wrote:
>> +/* Check if value C can be built by 2 instructions: one is 'li', another is
>> + rotldi.
>> +
>> + If so, *SHIFT is set to the shift operand of rotldi(rldicl), and *MASK
>> + is set
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80353
Andrew Pinski changed:
What|Removed |Added
CC||denis.yaroshevskij at gmail
dot co
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110303
Andrew Pinski changed:
What|Removed |Added
Resolution|--- |DUPLICATE
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110303
--- Comment #2 from Andrew Pinski ---
so _mm_shuffle_epi32 requires a constant but since it is an argument, the
argument, it is not a constant expression requirement.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110303
Andrew Pinski changed:
What|Removed |Added
Summary|In debug mode, gcc does not |Without -O0,
|force
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110303
Bug ID: 110303
Summary: In debug mode, gcc does not force compile time
evaluation for immediate arguments
Product: gcc
Version: 13.2.1
Status: UNCONFIRMED
This patch is a propsal patch is **NOT** ready to push since
after this patch the total machine modes will exceed 255 which will create ICE
in LTO:
internal compiler error: in bp_pack_int_in_range, at data-streamer.h:290
The reason we need to add VLS modes for following reason:
1. Enhance GNU
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86590
Jan Hubicka changed:
What|Removed |Added
CC||hubicka at gcc dot gnu.org
--- Comment
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110287
--- Comment #5 from Jan Hubicka ---
> Do you mean something like this?
I sent my own version, but yours looks nicer.
>
> diff --git a/libstdc++-v3/include/bits/stl_vector.h
> b/libstdc++-v3/include/bits/stl_vector.h
> index
Snapshot gcc-14-20230618 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/14-20230618/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 14 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
Add target into changelog:
PR target/110299
Otherwise, LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-18 23:13
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
From:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
Gaius Mulley changed:
What|Removed |Added
Status|RESOLVED|CLOSED
--- Comment #8 from Gaius Mulley
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58770
--- Comment #8 from Sam James ---
(See the thread at
https://inbox.sourceware.org/gcc-patches/6027e3bb-99f9-573b-ff5e-ea1a48882...@acm.org/.)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
Jakub Jelinek changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
Hi,
as noticed by Jeff, this patch also triggers warning in one of LTO
testcases. The testcase is reduced and warning seems legit, triggered
by extra inlining. So I have just silenced it.
Honza
gcc/testsuite/ChangeLog:
* gcc.dg/lto/20091013-1_0.c: Disable stringop-overread warning.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110301
--- Comment #2 from Andrew Pinski ---
OR:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4e31e63ea7edffd1212fc17ce8d50672035bb64b
But I don;t think that would change anything here.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110301
--- Comment #1 from Andrew Pinski ---
Maybe:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=ea616f687dccbe42012f786c0ebade5b05850206
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=710b8dec61a73cbbf5dadbdd2070a85e690e8184
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110301
Andrew Pinski changed:
What|Removed |Added
Summary|x264 regression on |[14 Regression] x264
Hi,
this patch extends ipa-fnsummary to anticipate statements that will be removed
by SRA. This is done by looking for calls passing addresses of automatic
variables. In function body we look for dereferences from pointers of such
variables and mark them with new not_sra_candidate condition.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110302
Bug ID: 110302
Summary: libquantum regression on zen3 with LTO and PGO
Product: gcc
Version: 13.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
--- Comment #6 from Gaius Mulley ---
ok to close?
gcc/ChangeLog:
* rtl.h (*rtx_equal_p_callback_function):
Change return type from int to bool.
(rtx_equal_p): Ditto.
(*hash_rtx_callback_function): Ditto.
* rtl.cc (rtx_equal_p): Change return type from int to bool
and adjust function body accordingly.
* early-remat.cc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110301
Bug ID: 110301
Summary: x264 regression on Neoverse-N1
Product: gcc
Version: 13.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
--- Comment #5 from CVS Commits ---
The master branch has been updated by Gaius Mulley :
https://gcc.gnu.org/g:24f75498ea59be94ae3eb1b82aa0b9de6ebfa232
commit r14-1911-g24f75498ea59be94ae3eb1b82aa0b9de6ebfa232
Author: Gaius Mulley
Date:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92887
anlauf at gcc dot gnu.org changed:
What|Removed |Added
Attachment #55356|0 |1
is obsolete|
David Malcolm via Gcc-patches writes:
> Quoting "How a computer should talk to people" (as quoted
> in "Concepts Error Messages for Humans"):
>
> "Various negative tones or actions are unfriendly: being manipulative,
> not giving a second chance, talking down, using fashionable slang,
> blaming.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95185
--- Comment #5 from Andrew Pinski ---
_1 = x_4(D) >= 0;
_2 = y_5(D) <= 0;
_3 = _1 == _2;
Something like:
Prefer ^ over ==
```
(for cmp
(for cmpN
(for neeq
(simplify
(neeq:c (cmp @0 @1) @3
(if (cmpN == inverseof(cmp, TREE_TYPE (type))
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
--- Comment #4 from Gaius Mulley ---
Also now bootstrapped successfully on ppc64le - so I'll git commit the changes.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53669
Andrew Pinski changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89582
Andrew Pinski changed:
What|Removed |Added
Summary|Suboptimal code generated |Suboptimal code generated
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95929
--- Comment #3 from Andrew Pinski ---
On the GCC 13+ we get:
_1 = a_5(D) != 0;
_8 = a_5(D) == 0; // _1^1
_2 = b_3(D) != 0;
_13 = _2 ? _8 : _1;
_6 = (int) _13;
or rather
_13 = _2 ? _1 ^ 1 : _1
But we don't match that.
We could
Hi,
_M_check_len is used in vector reallocations. It computes __n + __s but does
checking for case that (__n + __s) * sizeof (Tp) would overflow ptrdiff_t.
Since we know that __s is a size of already allocated memory block if __n is
not too large, this will never happen on 64bit systems since
On 6/15/23 09:30, Manolis Tsamis wrote:
Thanks for reporting. I also noticed this while reworking the
implementation for v2 and I have fixed it among other things.
Sounds good. I stumbled across another problem while testing V2.
GEN_INT can create a non-canonical integer constant (and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105512
David Truby changed:
What|Removed |Added
CC||gnu.w2nnu at simplelogin dot
com
---
Testing the V2 version of Manolis's fold-mem-offsets patch exposed a
minor bug in the arc backend.
The movsf_insn pattern has constraints which allow storing certain
constants to memory. reload/lra will target those alternatives under
the right circumstances. However the insn's condition
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110300
Andrew Pinski changed:
What|Removed |Added
Last reconfirmed||2023-06-18
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109849
--- Comment #15 from CVS Commits ---
The master branch has been updated by Jan Hubicka :
https://gcc.gnu.org/g:5a1ef1cfac005370d0a5a0f85798724cb2c9cf5e
commit r14-1909-g5a1ef1cfac005370d0a5a0f85798724cb2c9cf5e
Author: Honza
Date: Sun Jun
Hi,
we currently produce very bad code on loops using std::vector as a stack, since
we fail to inline push_back which in turn prevents SRA and we fail to optimize
out some store-to-load pairs (PR109849).
I looked into why this function is not inlined and it is inlined by clang. We
currently
From: Pan Li
The rvv widdening reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
--- Comment #3 from Jakub Jelinek ---
Comment on attachment 55359
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55359
Proposed fix
Except for the stor-layout changes that is what I was trying, so if it works,
great.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110284
Gaius Mulley changed:
What|Removed |Added
CC||gaius at gcc dot gnu.org
--- Comment #2
I was wondering whether I could ask a LRA/reload expert for their help with
a better fix with this issue.
For the testcase (from sse2-v1ti-mov-1.c):
typedef unsigned __int128 uv1ti __attribute__ ((__vector_size__ (16)));
uv1ti foo(__int128 x) { return (uv1ti)x; }
we currently generate (with
Thanks for cleaning up codes for future's ABI support patch.
Let's wait for Jeff or Robin comments.
Thanks.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-18 19:41
To: gcc-patches
CC: juzhe.zhong; yanzhang.wang; kito.cheng; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Add tuple vector
Thanks for fixing it for me.
LGTM now.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-18 10:57
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for RVV float reduction in ZVE32/64
From: Pan Li
The rvv integer
Hi,
On 6/15/23 17:03, Xi Ruoyao wrote:
Xuerui: I guess this makes it sensible to show "ret" instead of "jirl
$zero, $ra, 0" in objdump -d output, but I don't know how to implement
it. Do you have some idea?
Thanks for the suggestion! Actually I have previously made this patch
series [1]
Hi,
This patch does several things:
1. Adds the missed checking of tuple vector mode
2. Extend the scope of checking to all vector types, previously it
was only for scalable vector types.
3. Simplify the logic of determining code of vector type which will lower to
vector tmode
On Sun, Jun 18, 2023 at 11:35 AM Roger Sayle wrote:
>
>
> A patch that I'm working on to improve RTL simplifications in the
> middle-end results in the regression of pr78904-1b.c, due to changes in
> the canonical representation of high-byte (%ah, %bh, %ch, %dh) logic.
> This patch
On Sun, Jun 18, 2023 at 1:10 PM Roger Sayle wrote:
>
>
> This patch refactors the three places in the i386.md backend that we
> set the carry flag into a new ix86_expand_carry helper function, that
> allows Jakub's recently added uaddc5 and usubc5 expanders
> to take advantage of the recently
On Sun, Jun 18, 2023 at 11:05 AM Roger Sayle wrote:
>
>
> This clean-up improves consistency within i386.md by using QImode for
> the constant shift count in patterns that specify a mode.
>
> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
> and make -k check, both with and
This patch refactors the three places in the i386.md backend that we
set the carry flag into a new ix86_expand_carry helper function, that
allows Jakub's recently added uaddc5 and usubc5 expanders
to take advantage of the recently added support for the stc instruction.
This patch has been tested
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110300
Bug ID: 110300
Summary: Template disambiguator accepted for non-template
function
Product: gcc
Version: 13.1.0
Status: UNCONFIRMED
Severity: normal
An x86 backend improvement that I'm working results in combine attempting
to recognize:
(set (reg:DI 87 [ xD.2846 ])
(ior:DI (subreg:DI (ashift:TI (zero_extend:TI (reg:DI 92))
(const_int 64 [0x40])) 0)
(reg:DI 91)))
where the lowpart SUBREG
Hi, this is my first time with open source development. I worked in
automotive for 22 years and we (generally) were using tricore series for
these products. GCC doesn't compile on that platform. I left my work some
days ago and so I'll have some spare time in the next few months. I would
like to
A patch that I'm working on to improve RTL simplifications in the
middle-end results in the regression of pr78904-1b.c, due to changes in
the canonical representation of high-byte (%ah, %bh, %ch, %dh) logic.
This patch avoids/prevents those failures by adding support for the
alternate
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299
Bug ID: 110299
Summary: RISC-V: ICE when build RVV intrinsic widen with
"-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and
13.
Product: gcc
Version: 14.0
This clean-up improves consistency within i386.md by using QImode for
the constant shift count in patterns that specify a mode.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures. Ok for
It used to always return a constant 4, which is same as the default
behavior, but doesn't take into account the effects of secondary
reloads.
Therefore, the implementation of this target hook is removed.
gcc/ChangeLog:
* config/xtensa/xtensa.cc
(TARGET_MEMORY_MOVE_COST,
This patch adds a new 2-instructions constant synthesis pattern:
- A non-negative square value that root can fit into a signed 12-bit:
=> "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax"
Due to the execution cost of the integer multiply instruction (MULL), this
synthesis works only when the 32-bit
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