On Thu, Aug 04, 2022 at 03:53:55PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Aug 04, 2022 at 01:48:51PM -0400, Michael Meissner wrote:
> > At the moment, GCC 12 on the server PowerPC systems supports multiple
> > 128-bit
> > floating point types:
> >
&g
On Thu, Aug 04, 2022 at 10:14:10PM +0100, Jonathan Wakely wrote:
> On Thu, 4 Aug 2022 at 18:58, Michael Meissner via Gcc wrote:
> >
> > On Thu, Aug 04, 2022 at 10:49:24AM +0200, Nathan Sidwell wrote:
> > > Not a problem. I don't think I have anything to add- I presu
ompiled with previous GCC's that use explicit __ibm128 and
__float128 keywords. I don't how the users of these keywords (i.e. typically
libstdc++ and glibc developers, but potentially others as well).
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
them as
full fledged types, or are they just convenient ways to compile code with both
names rather than building two modules, with the different long double types?
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
evious GCC's that use explicit __ibm128 and
__float128 keywords. I don't how the users of these keywords (i.e. typically
libstdc++ and glibc developers, but potentially others as well).
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
i to the options as well as
-mabi={ieee,ibm}longdouble. This suppresses the warning that says you are
changing the long double type. If you have configred GCC against GLIBC 2.32 or
newer, then you don't need the -Wno-psabi option. Unfortunately, you can't use
-Wno-psabi on languages like Fortran.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
y to force long double to be IBM 128-bit, no matter what the defaults
are use:
-mabi=iibmlongdouble -Wno-psabi -mno-gnu-attribute
The no-gnu-attribute says to disable setting the GNU attribute that says what
the default long double type is. It is necessary when building libraries with
both 128-
ubious joys of dynamic linking and use
> -static-libgfortran instead.
Yes, I tend to use -static-libgfortran for running Fortran spec things, and
-static-libstdc++ for C++, since it can be a quaqmire getting the right library
when you have several libraries on the system.
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Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
in is to get access to newer libraries. I don't know
Ubuntu at all, but I believe the version that is installed is too old to have
the necessary changes in it. There isn't a LTS (long time support) version of
Ubuntu yet available that has the library. There are newer versions that
are
that is pointed to
# is incomplete. The msgfmt program then aborts because it doesn't have the
# right symbols. This script allows us to not use those environment variables.
unset LD_LIBRARY_PATH
unset RPATH_ENVVAR
for x in /usr/local/bin /usr/bin /bin; do
if [ -x "${x}/msgfmt"
On Mon, Nov 01, 2021 at 10:56:33AM -0500, Bill Schmidt wrote:
> Would starting from Advance Toolchain 15 with the most recent glibc make
> things easier for Thomas to test?
The problem is gcc135 runs Centos 7.x which is not compatible with AT 13-15.
--
Michael Meissner, IBM
PO Box 98
d glibc 2.34
or later.
> From 80d617264d80eb86806aecb2db5f37adb9b37ff6 Mon Sep 17 00:00:00 2001
> From: Michael Meissner
> Date: Fri, 29 Oct 2021 18:35:42 -0400
> Subject: [PATCH] Second patch for PowerPC Fortran KIND=16.
This replaces the first patch, and it is a work in progress. This patch
adds three target
ies, because I get messages like you get.
I have a new version of the patch that makes new target hooks to allow the
backend to specify KIND numbers for types. I choose kind=16 to always be IEEE
128-bit, and kind=15 to be long double if long double is IBM (since I
discovered yesterday, Fortran n
thought it would be useful to share what I've done.
> From 443773ac040383311384577b48ecc0bd957ff328 Mon Sep 17 00:00:00 2001
> From: Michael Meissner
> Date: Thu, 28 Oct 2021 23:23:53 -0400
> Subject: [PATCH] Initial patch for PowerPC Fortran KIND=16
This is a work in progress pa
ailures, due to
libgfortran still being marked as IBM long double and the fortran modules are
marked as IEEE long double.
Right now, the only way to avoid these things is to build the entire toolchain
defaulting to IEEE 128-bit.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 014
On Thu, Oct 07, 2021 at 08:08:21AM +0200, Thomas Koenig wrote:
> On 07.10.21 05:35, Michael Meissner via Fortran wrote:
> > I tried this at one point. There are a lot of hidden assumptions that the
> > kind
> > number is the number of bytes. I'm sure it can be tracked
ld be nice if
any distro that changed the default used power9 as a base, instead of power8.
> Converting double-double to IEEE QP should not be hard or slow?
There are a lot of corner cases to get it right. IIRC, there are a few values
that double double can represent that are not expressable with exact precision
in IEEE 128-bit.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
support for the
LE systems. If there is BE glibc support, we could certainly add support for
enabling IEEE 128-bit in BE systems if the compiler was configured for power8
or higher.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Tue, Sep 29, 2020 at 05:34:55PM +0100, Jonathan Wakely wrote:
> On Mon, 28 Sep 2020 at 23:15, Joseph Myers wrote:
> >
> > On Mon, 28 Sep 2020, Michael Meissner via Gcc wrote:
> >
> > > > I'm not sure which patch in the series is supposed to be implemen
On Mon, Sep 28, 2020 at 04:38:51PM +, Joseph Myers wrote:
> On Thu, 24 Sep 2020, Michael Meissner wrote:
>
> > As per the discussion in this thread, I did decide to keep things to two
> > types
> > within the compiler. This means that an explicit __float128 or _Fl
the same type node and TFmode as long double uses if the default for long
double is IEEE 128-bit.
https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554765.html
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1
On Wed, Sep 09, 2020 at 02:42:36PM +0100, Jonathan Wakely wrote:
> Sorry for the slow reply to this.
>
> On Fri, 7 Aug 2020 at 22:14, Michael Meissner wrote:
> >
> > One issue with doing the transition is what mangling should be used with the
> > new long double.
version of libgfortran, but we would
> have to restrict that to POWER (would that be possible?).
> We cannot impose an ABI change on everybody else to this.
We do annotate each function that has long double arguments or returns long
double arguments already with gnu attributes. There are some issues with it,
and I want to delve into it deeper.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
;g" if long double is IBM
long double "u12_ieee128_ld"if long double is IEEE
__float128 "u9__ieee128"
__ibm128"g"
If we decide to change the __ibm128 mangling (or the long double when long
double i
support TImode on 32-bit systems. Some
parts of GCC require a supported integer that is the same size as basic types.
If somebody is motivated to do that work, that is fine, but I'm not planning to
do that work.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, M
> uint16_t param1;
> ...
> }
> }
This definately requires support at the higher levels of the compiler.
> and then I could access data in little ordering in the structures, then
> in 16-bit big-endian lumps via the "protocol" array.
One of the things you have to do is be prepared to do a full sweep of your
backend to make sure you only used the named address memory functions and don't
use the traditional functions that pass 0 for the named address.
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Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
On Fri, May 05, 2017 at 01:38:03PM -0700, Evgeny Stupachenko wrote:
> On Fri, May 5, 2017 at 12:48 PM, Michael Meissner
> wrote:
> > On Fri, May 05, 2017 at 12:32:03PM -0700, Evgeny Stupachenko wrote:
> >> Hi Michael,
> >>
> >> On Fri, May 5, 2017 at
On Fri, May 05, 2017 at 12:32:03PM -0700, Evgeny Stupachenko wrote:
> Hi Michael,
>
> On Fri, May 5, 2017 at 11:45 AM, Michael Meissner
> wrote:
> > This message is separated from the question about moving code, as it is a
> > questions about the functionality
}
__attribute__((target_clones("default","avx","avx2")))
int callee (void)
{
return 10;
}
I.e. caller.avx should call callee.avx, not callee (or callee.ifunc), and
caller.avx2 should call callee.avx2. Do people thin
.type foo.avx.0, @function
foo.avx.0:
movl$10, %eax
ret
.type foo.avx2.1, @function
foo.avx2.1:
movl$10, %eax
ret
Note, it does not generate the resolver at all.
--
Michael Meissner, IBM
IBM, M/S 2506
t strings of the function decls are
different. This assumes that FN1 and FN2 have the same signature.
This is the TARGET_OPTION_FUNCTION_VERSIONS target hook, and it is the
same between the x86 and ppc.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littlet
floating point and use IEEE 128-bit instead of
IBM double-double that the other PowerPC systems currently use.
So it may be your call whether you want to enable it, and get it to work, or
default back to long double == double.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
On Mon, Apr 25, 2016 at 11:04:01AM -0600, Jeff Law wrote:
> On 04/21/2016 01:53 PM, Michael Meissner wrote:
> >As I start to allow integer modes into vector registers, I need to revisit
> >MODES_TIEABLE_P. I'm wondering if MODES_TIEABLE_P is transitive?
> I don'
other. And does it matter
whether we are using RELOAD or IRA?
Thanks in advance.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
ad instruction that uses the constant
as an index register.
Future machines may expand upon the list of fusable instructions.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
.org/wiki/RS/6000
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
g from). From this distance, it sure
looks like a bug, but I'm not sure whether it should be fixed or grand-fathered
in (and updating the stdargs.h support, if this is the offical calling
sequence).
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
tup time
(like the PowerPC does), you have to define all of the types used, even the
current switches don't allow use of the types. Or you can only define what you
need, and when you change options, you go through and define any stuff that
wasn't previously defined that you can now use (like the current x86_64).
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
proprosed
(such as __float128)?
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
to
create an alternate floating point mode than FRACITION_FLOAT_MODE that does no
automatic widening. If there is a way under the current system, I am not aware
of it.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phon
d the other for more recent customers?
I don't have a handle on the need for IEEE 128-bit floating point in non-server
platforms. I assume in these environments, if we need IEEE 128-bit, it will be
passed as two floating point values. Do we need this support?
--
Michael Meissner, IBM
IBM, M/S
of the user inadvertently calling the wrong function.
As I see it, we have a choice to have something like multilibs where you select
which library to use, or we have to use alternate names for all of the IEEE
128-bit emulation functions.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street
t (vxworks?).
In terms of places where TFmode is mentioned in GCC, it is the following files:
predicates.md, rs6000.c, rs6000.h, rs6000.md, rs6000-modes.def, spe.md
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phon
have
to move to a compiler/library combination for a feature they don't use.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
ded
into 3 camps, one that wanted to delete enums altogether, one that wanted them
as int constants, and one that wanted more type checking.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
or different
registers.
Unfortunately the first machines GCC originally targeted (68k, vax) had general
addressing formats that worked everywhere, and later machines you knew for a
given type what type of addressing could be used.
In the PowerPC you don't want register+offset if you are target
>
> #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)"
>
>
> --
> Alan Modra
> Australia Development Lab, IBM
>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
is no longer
relevant.
Another way to go is what we do in 64-bit powerpc -- function pointers are
actually pointers to a 3 word descriptor, that contains the real function
address, the value to load into the GOT pointer, and the value to load into the
register holding the static chain.
--
Michael
bi = 1; \
> } \
>
> That compiles but I wanted a sanity check that it is the right
> transformation.
Yes, this is the right transformation. Here is an untested patch that fixes
it:
2011-11-08 Michael Meissner
* config/rs6000/rtems.h (SUBSUBTARGE
ere recently added to
> gcc/configure.ac and libcpp/configure.ac.
FWIW, I'm seeing it also when I'm building on x86_64 RHEL 6.1 targeting
powerpc64-linux, so I suspect it is a cross compiler issue, but I haven't
checked it in detail.
--
Michael Meissner, IBM
5 Technology Place Drive,
hen I'm
doing this, I tend to prefer eliminating any -j options so that it is clearer
what is going on.
To simplify things that break in libgcc, I often times just configure for C
only, just to save the build time.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
> return false;
> }
>
>
> I choose .asmcons because it runs between IRA and split1,
> and because I observed that pass numbers are fuzzy;
> presumably because sub-passes like df etc.
I'm not a big fan of this. I think it would be better to just add
ira_in_progress and a fe
_insn_and_split "*mulsqihi3_const2"
[(set (match_operand:QI 0 "register_operand" "r")
(match_operand:QI 1 "u8_operand" "n"))
(set (match_operand:HI 2 "register_operand" "r")
(mult:HI (sign_extend:HI (match_operand:QI 3 "register_operand" "a"))
(zero_extend:HI (match_dup 0]
"AVR_HAV_MUL"
"#"
"&& reload_completed"
[(set (match_dup 0)
(match_dup 1))
(set (match_dup 2)
(mult:HI (sign_extend:HI (match_dup 3))
(zero_extend:HI (match_dup 0]
{})
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
ings has my paper describing adding the named
address space support to the compiler. Note I have moved groups within IBM,
and no longer work on the SPU compiler, so I haven't touched the named address
space support since the early part of 2009.
http://gcc.gnu.org/wiki/HomePage?action=Attach
I would like to add similar support in GCC.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
lace those two arrays (with GET and SET
versions), and poison the old usage.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
mpiler also figure out vector operations by itself during the
> optimization phase of compilation?
If -msse2 is used on the command line or inside of a target attribute/pragma,
the compiler feels free to use the sse2 instructions in any fashion, including
when vectorizing.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
gave the talk on named address spaces I mentioned this,
and during the summit last year, I made a toy demonstration set of patches in
the PowerPC to add cross endian support.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
> No, it is a code quality problem. And yes, I have seen actual
> SH patterns being recognized that were not wanted, and lead to worse
> code overall.
Generally you need to tighten the pattern conditions to make sure it doesn't
match.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
eg:SF 126)
(reg:SF ACC_REGISTER)))
So whether the passes in between combine and the split pass care, is a
different question. I didn't recall that combine had this split feature. As I
said, my preference is to create the insn, and then split it later.
Note, you can only allocate new registers (either hard registers or pseudo
registers) in the split passes before register allocation. You will get an
error if you create a new register after reload.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
st
is approved for builtin functions).
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
he assembler/linker/debugger/library. However, note that I have been
working on GCC for quite some time, and have done at least 5 ports from
scratch, so you probably don't want to use my time estimates :-)
The more irregular/limited the machine is, the more it takes to get reasonable
code gene
ill emit the special insn just if optimization is turned on, but nevertheless
> it would be interesting to know why this works smooth with -O0 as I expected
> to
> run in unrecognizable insn or something like that during reload).
In gcc/passes.c the split passes are always run and do not depend on the
optimization flags, so yes, you can now rely on it with -O0.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
4)
(match_dup 3)))
(set (match_dup 0)
(match_dup 4))]
"operands[4] = gen_rtx_REG (SFmode, ACC_REGISTER);")
In the old days, define_split was only processed before each of the two
scheduling passes if they were run and at the very end
On Thu, Oct 21, 2010 at 08:17:51PM +0200, Gunther Nikl wrote:
> Michael Meissner wrote:
> > Note, the 64-bit ABI requires that r2 have the current function's GOT in it
> > when the function is called, while the 32-bit ABI uses r2 as a small data
> > pointer (and possibly
by doing call to the next instruction to get
the address in the LR.
So, it isn't as simple as moving the the 64-bit stuff in 32-bit, since there
are different assumptions.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
f the address happens to be defined in the current program unit (main program
or shared librar), the linker can transform this to:
addis ,r2,la...@toc@ha
addi ,,la...@toc@l
or:
nop
addi ,r2,la...@toc@l
or:
nop
ld ,la...@got@l(r2)
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
On Wed, Aug 18, 2010 at 12:56:47PM -0700, Richard Henderson wrote:
> On 08/18/2010 12:06 PM, Michael Meissner wrote:
> > Now, unfortunately, I've been away from the code for about 2 years, and I
> > don't
> > know whether it has bit-rotted or not.
>
&g
unction. This does the target_reinit and eventually
reinit_regs.
Now, unfortunately, I've been away from the code for about 2 years, and I don't
know whether it has bit-rotted or not.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com
ools to
convert cvs to svn (such as cvs2svn), but I haven't used them personally.
http://svnbook.red-bean.com/en/1.0/apas11.html
--
Michael Meissner, IBM
Until June 30: 4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
After June 30: 5 Technology Place Drive, MS 2757, Westford, MA 01886, USA
meiss...@linux.vnet.ibm.com
As I was about to check in the -mrecip changes for powerpc on GCC 4.6, I
figured to get a start on documentation, and I was going to edit the
gcc-4.6/changes.html file. I realize this is early in the cycle, but did we
want to create the gcc-4.6 directory?
--
Michael Meissner, IBM
Until June 30
something like a "register_target_extensions" callback
> in targetcm, but that can probably be done in a separate patch.
Note, many of the things done by REGISTER_TARGET_PRAGMAS deal with the
preprocessor and keywords, which are used by the C-like front ends, but not
used for Ada, For
et up the keywords. The target hook would have to duplicate the
functionality of all of the setup that c_parse_init and init_reswords do,
particularly if they have different semantics.
--
Michael Meissner, IBM
Until June 14: 4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
A
ll compilers have the notion of a vector keyword that
is followed by a type (powerpc needs -maltivec and/or -mvsx to enable it). So
you can write:
vector float sum (vector float a, vector float b) { return a+b; }
Now, ideally, it would be useful to have sytax so you could change the vector
size,
need to change as true filenames based on
> source/object files.
Well if this is a big problem for you, when 4.6 opens up, feel free to add a
new varient of -save-temps=. The current implementation of
-save-temps=obj meets the needs that I had in doing large builds.
> - "-save-temp
en it has been in the
compiler for 2 years now. There were a number of people that did ask me for it
when I presented the initial thoughts a few years ago.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
te, VMX is the
altivec instruction set, not the new power7 (VSX) instruction set. Power6
machines should have altivec support.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
do for GCC?
So roll up your sleeves and get coding, or convince other people (and their
managers) that it is a good thing to do. I suspect there are people starting
to think about it, and perhaps the interested parties need to organize to scope
out the work.
--
Michael Meissner,
c
>
> Should the format string warnings really be complaining about this on a
> platform (i686-pc-cygwin) where there's only one kind of pointer? I don't get
> the rationale, if this is intentional.
Yes. It still is a type violation, even if it will work
s available, and the new registers do not
have hard wired uses, which in the past always meant a lot of spills (also, the
default floating point unit is SSE instead of the x87 stack). I never got
around to testing this before AMD and I parted company.
> On PPC -fschedule-insns is normally benefic
On Thu, Jul 02, 2009 at 06:54:52PM -0400, Ken Raeburn wrote:
> On Jul 2, 2009, at 16:44, Michael Meissner wrote:
>> Anyway I had some time during the summit, and I decided to see how
>> hard it
>> would be to add explicit big/little endian support to the powerpc
>> p
int *__little bar = &foo;
would declare bar to be a normal pointer, which points to a little endian
item. The following would be illegal, since bletch and bar point to different
named address spaces, and the backend says you can't convert them.
int *bletch = bar;
--
Michae
orts would be rejected for
formatting in some of the files). I don't recall having any problems with the
machine independent changes.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
for approval. I sent mail to the
list Tom Tromey mentioned in the followup, but I haven't seen a reply yet.
http://gcc.gnu.org/ml/gcc-patches/2009-06/msg01094.html
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
On Sat, Jun 13, 2009 at 08:14:36PM -0700, Steve Kargl wrote:
> Someone has broken gfortran on FreeBSD with dwarf debugging.
> This is a regression. Please fix!
I just wrote a patch to fix this:
http://gcc.gnu.org/ml/gcc-patches/2009-06/msg01097.html
--
Michael Meissner, IBM
4 Technology
search for '.md' and there are tons of examples.
> Although, I was curious if there was a generic template.
Many years ago, I wrote a generic machine that was intended to be a template
for this, but it quickly became out of date and useless. I'm not aware of a
more modern versi
ar, that I don't
remember all of the details of why particular choices were made.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
ibute so the programmer can
> mark the pointer as non overlapping and push the problem onto them.
> Something clever would be nice though :)
Another place where the named address spaces stuff I worked on last year might
be useful.
> Sorry for all the questions - this is quite a difficult
e.
> But now I get and invalid rtx sharing from the push/pop parallels:
>
>
> .c: In function 'test_dashr':
> .c:32: error: invalid rtl sharing found in the insn
> (insn 26 3 28 2 .c:26 (parallel [
> (insn/f 25 0 0 (set (reg/f:SI 51 SP)
> (minus:SI (reg/f:SI 51 SP)
> (const_int 4 [0x4]))) -1 (nil))
> (set/f (mem:SI (reg/f:SI 51 SP) [0 S4 A8])
> (reg:SI 8 r8))
> ]) -1 (nil))
> .c:32: error: shared rtx
> (insn/f 25 0 0 (set (reg/f:SI 51 SP)
> (minus:SI (reg/f:SI 51 SP)
> (const_int 4 [0x4]))) -1 (nil))
> .c:32: internal compiler error: internal consistency failure
I suspect you don't have the proper guards on the push/pop insns, and the
combiner is eliminating the clobber. You probably need to have parallel insns
for the push and pop.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
re.
Yes, it was added in GCC 4.4. It might make sense to start the rebase to the
current mainline (you will need to do it sooner or later, and it becomes more
painful the further away the code is).
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
LASS, then the compiler assumes each
register class is unique, and it can't copy between them.
I ran into this on the power7 support. On previous power machines, you have
two classes of registers FLOAT_REGS and ALTIVEC_REGS (in addition to the GPRs
and other registers), but the new VSX instruction set has a merged register set
that both the traditional floating point registers and the altivec vector
registers are a set of. I found I needed to have a different cover class for
VSX using the VSX_REGS class which is the union of the two, and FLOAT_REGS,
ALTIVEC_REGS for the pre-vsx code, and switch which is used in the
ira_cover_classes target hook.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
r the appropriate create a builtin function in external scope
hook.
However, that still leaves the compiler creating a lot of builtins that mostly
aren't used. It may be useful to register names, and have a call back to
create the builtin if the name is actually used. It certainly would e
I, RS6000_BTI_V16QI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
RS6000_BTI_V4SF, RS6000_B
.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
oad, and need to delve into the mysteries of secondary reload.
I would imagine that for pointer sized things it is best if you do need to
implement multiple instructions that you hold off on splitting until after
reload is completed.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
ure). In particular, shifts done in the general
purpose registers were not truncated, but vector shifts done in the SSE5
instructions were truncated (or vice versa).
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
tance, this was one of the first links I found with
looking for 'matrix multiple cache'
http://www.cs.umd.edu/class/fall2001/cmsc411/proj01/cache/index.html
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
vector shift, preferably both types.
>
> Bingfeng
It shouldn't be too hard to add the support. I suspect the person who did the
initial support may have been on a machine without vector shifts.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
of machines.
If the machine only has vector shift by a scalar, the auto vectorizer will not
generate a vector shift for:
for (i = 0; i < n; i++)
a[i] = b[i] << c[i]
Internally, the compiler uses the standard shift names for vector shift by a
scalar (i.e. ashl, ashr, lshl
r instruction definition, if I use the first
> solution (match_dup), the instruction that will calculate the
> input/output operand 0 sometimes gets removed by the web pass. But if
> I use the second solution (put a "0" constraint), then it is no longer
> removed. Any idea why these two definitions would be treated
> differently in the web pass?
I don't know much about the web pass, however as I said, the two definitions
are fundamentally different.
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meiss...@linux.vnet.ibm.com
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