On Sat, 2008-01-26 at 08:39 -0800, David Daney wrote:
> I have tried several times (and failed) to run the GCC testsuite on
> multilib targets (x86-64 and mips64) and have not been able to figure
> out how to get more that a single multilib configuration to be tested.
> The instructions on http:/
On Wed, 2008-01-23 at 12:06 +0100, Richard Guenther wrote:
> As we now reached the goal of less than 100 open serious regressions
> against GCC 4.3, we are as of now in regression and documentation fixes
> only mode. This means that for patches going on the trunk the same
> rules as for release br
On Sun, 2007-12-30 at 10:16 +0100, Gerald Pfeifer wrote:
> At http://www.gnu.org/software/gcc/extensions.html we have a reference
> to the DLX port of GCC, which corresponds to the DLX machine described
> in "Computer Architecture: A Quantitative Approach" by Hennessy and
> Patterson.
>
> Sadly,
On Tue, 2007-09-04 at 19:40 -0700, Mark Mitchell wrote:
> Are there Stage 1 or Stage 2 patches in need of review? I'll do my best
> to either (a) convince someone to review them, or (b) review them myself.
It has only been four days since I posted the patch, but I am
waiting for a review of the n
As a somewhat related follow on to Kenny's new interference graph
builder patch (which is still waiting for a full review):
http://gcc.gnu.org/ml/gcc-patches/2007-08/msg01729.html
I'd like to squeeze in a new representation of the interference graph
that in some cases can save a significant a
On Fri, 2007-08-17 at 09:32 -0400, Kenneth Zadeck wrote:
> The problem comes where you have a store that uses 2 or more hard regs
> but one or more of those hardregs is unused.
>
> In a forwards scan, ALL of the set regs will interfere with anything
> live until the last set reg goes dead. In a b
On Sat, 2007-06-02 at 07:35 -0700, H. J. Lu wrote:
> When was decimal floating point added to gcc? I couldn't find it
> in any gcc changes.html. Shouldn't it be mentioned somewhere?
I think these were the merges from the dfp-branch:
http://gcc.gnu.org/ml/gcc-patches/2005-11/msg01919.html
http
On Tue, Nov 07, 2006 at 11:36:00PM -0600, Peter Bergner wrote:
> The parallel that is causing the ICE is a store with update RTL insn.
> It seems like we should detect that and reach into the parallel and
> grab the actual store insn. I'll look into adding that.
I'm testing t
> for over a week, so do not know when this was introduced...
>
> This was introduced by:
> 2006-11-01 Pete Steinmetz <[EMAIL PROTECTED]>
> Peter Bergner <[EMAIL PROTECTED]>
>
> * doc/invoke.texi: Add cpu_type power6x
>
> The function
On Fri, 2006-09-22 at 08:53 -0500, Peter Bergner wrote:
> On Fri, 2006-09-22 at 09:33 -0400, Jack Howarth wrote:
> > Peter,
> > Looking at the libffi/src/powerpc/ffi.c file, I assume that
> > I should have the same...
> >
> >*next_arg++ = (unsigned long)
On Fri, 2006-09-22 at 09:33 -0400, Jack Howarth wrote:
> Peter,
> Looking at the libffi/src/powerpc/ffi.c file, I assume that
> I should have the same...
>
>*next_arg++ = (unsigned long)(char *)ecif->rvalue;
>
> in ffi_darwin.c instead of the current...
>
>*next_arg++ = (unsigned)(ch
On Thu, 2006-09-21 at 23:54 -0400, Jack Howarth wrote:
> We have
> the same issue in gcc-4.2-20060915/libffi/src/powerpc/ffi_darwin.c
> (which might explain why it fails so many tests at -m64).
>
> http://gcc.gnu.org/ml/gcc/2006-09/msg00277.html
For this thread, you have:
*next_arg++ = (uns
On Thu, 2006-09-21 at 23:54 -0400, Jack Howarth wrote:
> Peter,
> Wouldn't we want something like...
>
> +#ifdef __powerpc64__
> +unsigned long FindTopOfStack(unsigned long stack_start) {
> +#else
> unsigned long FindTopOfStack(unsigned int stack_start) {
> +#endif
Why have the #ifdef? Why
On Thu, 2006-09-21 at 23:06 -0400, Jack Howarth wrote:
> Andrew,
> I've been trying to get a handle on why the line...
>
> frame = (StackFrame *)stack_start;
>
> in gcc/boehm-gc/darwin_stop_world.c only generates the warning...
>
> ../../../../gcc-4.2-20060920/boehm-gc/darwin_stop_world.
ith the tag
+ [ra-improvements] in the subject line. The branch
+ is maintained by mailto:[EMAIL PROTECTED]">Peter
+ Bergner.
Architecture-specific
On Wed, 2005-11-23 at 15:05 +0100, Michael Matz wrote:
> > Spill Cost Engine [page(s) 26-29]:
> > * The register allocator should not be estimating the execution
> > frequency of a basic block as 10^nesting level. That information
> > should be coming from the cfg which comes from
On Tue, 2005-11-22 at 22:56 +0100, an unknown sender wrote:
> On Tuesday 22 November 2005 20:26, Peter Bergner wrote:
> > Insn Annotations [page(s) 17-18]:
> > * I like the idea of easy access to the register usage info
> > provided by the insn annotations. R
On Thu, 2005-11-17 at 11:53 -0500, Andrew MacLeod wrote:
> I have been contemplating building a GCC register allocator from scratch
> for some time. To that end, I have put together a bit of a document
> given a high level overview of the various components I think would
> benefit GCC, and a rough
On Wed, 2005-08-24 at 00:07 -0400, Daniel Berlin wrote:
> I imagine if you have 300k bb's or 1.5 million live pseudos to consider,
> it probably makes a real difference, but that's not *too* common in our
> supported languages (30k bb's/150k pseudos is probably the practical
> upper limit of what w
the idea: "Register allocation method
and apparatus for truncating runaway lifetimes of program variables
in a computer system". I have no idea whether this was one of the
patents made available by IBM for use by the OSS community or not.
Peter
--
Peter Bergner
Linux on Power Toolchain
IBM Linux Technology Center
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