https://gcc.gnu.org/g:cff270707f107aff207f4afa73092a2d0731b032
commit r14-10411-gcff270707f107aff207f4afa73092a2d0731b032
Author: YunQiang Su
Date: Thu Jul 11 20:43:54 2024 +0800
RISC-V: NO_WARNING preferred else value for RVV
PR target/115840
https://gcc.gnu.org/g:c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd
commit r15-1995-gc6f38e5e6d900b8ed6a4f5c126d3197946cad4dd
Author: YunQiang Su
Date: Thu Jul 11 20:43:54 2024 +0800
RISC-V: NO_WARNING preferred else value for RVV
PR target/115840
Richard Biener 于2024年7月11日周四 20:21写道：
>
> On Thu, Jul 11, 2024 at 2:13 PM YunQiang Su wrote:
> >
> > From: YunQiang Su
> >
> > PR target/115840.
> >
> > In riscv_preferred_else_value, we create an uninitialized tmp var
> > for else value, i
From: YunQiang Su
PR target/115840.
In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.
The problem is that `warn_uninit` will emit
From: YunQiang Su
Uninitialized internal temp variable may be useful in some case,
such as for COND_LEN_MUL etc on RISC-V with V extension: If an
const or pre-exists VAR is used, we have to use "undisturbed"
policy; if an uninitialized VAR is used, we can use "agnostic&q
From: YunQiang Su
PR target/115840.
In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.
The problem is that `warn_uninit` will emit
Ping again.
https://gcc.gnu.org/g:320c2ed4d2b4b007bab5ebf0078e6c730ad25d3e
commit r15-1852-g320c2ed4d2b4b007bab5ebf0078e6c730ad25d3e
Author: YunQiang Su
Date: Thu Jun 27 18:28:27 2024 +0800
MIPS: Support more cases with alien mode of SHF.DF
Currently, we support the cases that strictly fit
We have done so for MIPSr6, which removes the support of condtional
trap with IMM. To be consistent, Let's do so for pre-R6.
We also add 2 new tests
1) be sure that $0 is used.
2) be sure we expand the condtional trap compare with constant,
instead of leaving it to GAS.
We decide to so so
https://gcc.gnu.org/g:33dfd6798aa3e5f8be58c8810f9814d57485fe12
commit r15-1851-g33dfd6798aa3e5f8be58c8810f9814d57485fe12
Author: YunQiang Su
Date: Thu Jun 27 18:05:30 2024 +0800
Testsuite/MIPS: Fix msa.c: test7_v2f64, test7_v4f32, test43_v2i64
BNEGI.W/D are used for test7_v2f64
https://gcc.gnu.org/g:e08ed5f1c98ea8de086f5c2d1e373aec6e195735
commit r15-1850-ge08ed5f1c98ea8de086f5c2d1e373aec6e195735
Author: YunQiang Su
Date: Fri Jun 28 10:08:38 2024 +0800
MIPS/testsuite: Add -mfpxx to call-clobbered-1.c
The scan-assembler-times rules only fit for -mfp32
https://gcc.gnu.org/g:f1437b96029d78e72bd987997f5303e29ebbb9f0
commit r15-1849-gf1437b96029d78e72bd987997f5303e29ebbb9f0
Author: YunQiang Su
Date: Fri Jun 28 16:11:35 2024 +0800
MIPS/testsuite: Fix umips-save-restore-1.c
With some recent optimization, -O1/-O2/-O3 can archive
With some recent optimization, -O1/-O2/-O3 can archive almost same
performace/size by stack load/store. Thus lwm/swm will save/store
less callee-saved register. In fact only $16 is saved with swm.
To be sure that this optimization does exist, let's add 2 more
function calls. So that lwm/swm
The scan-assembler-times rules only fit for -mfp32 and -mfpxx.
It fails if we are configured as FP64 by default, as it has
one less sdc1/ldc1 pair.
gcc/testsuite
* gcc.target/mips/call-clobbered-1.c: Add -mfpxx.
---
gcc/testsuite/gcc.target/mips/call-clobbered-1.c | 2 +-
1 file changed,
Currently, we support the cases that strictly fit for the instructions.
For example, for V16QImode, we only support shuffle like
(0<=N0, N1, N2, N3<=3 here)
N0, N1, N2, N3
N0+4N1+4N2+4, N3+4
N0+8N1+8N2+8, N3+8
N0+12 N1+12 N2+12,
BNEGI.W/D are used for test7_v2f64 and test7_v4f32 now. It is
an improvment since that we can save a instruction.
ILVR.D is used for test43_v2i64 now, instead of INSVE.D.
gcc/testsuite
gcc.target/mips/msa.c: Fix test7_v2f64, test7_v4f32 and
test43_v2i64.
---
Maciej W. Rozycki 于2024年6月28日周五 01:01写道：
>
> On Thu, 27 Jun 2024, YunQiang Su wrote:
>
> > > The missed optimisation in GAS, which used not to trigger pre-R6, is
> > > irrelevant from this change's point of view and just adds noise. I'm
> > > surprised th
Maciej W. Rozycki 于2024年6月27日周四 00:07写道：
>
> On Thu, 20 Jun 2024, YunQiang Su wrote:
>
> > MIPSr6 removes condition trap instructions with imm, so the instruction
> > like `teq $2,imm` will be converted to
> > li $at, imm
> > teq $2, $at
> >
> > Th
Just FYI. This patch does something to gcc.target/mips/madd-8.c, and
gcc.target/mips/msub-8.c.
-PASS: gcc.target/mips/madd-8.c -O2 scan-assembler \tmul\t
-PASS: gcc.target/mips/madd-8.c -O2 scan-assembler-not \tmadd\t
-PASS: gcc.target/mips/madd-8.c -O2 scan-assembler-not \tmflo\t
https://gcc.gnu.org/g:0b456434fe0f1d64291b7c6b3596c836c9519f85
commit r15-1604-g0b456434fe0f1d64291b7c6b3596c836c9519f85
Author: YunQiang Su
Date: Wed Jun 19 23:48:26 2024 +0800
MIPS: Output $0 for conditional trap if !ISA_HAS_COND_TRAPI
MIPSr6 removes condition trap instructions
https://gcc.gnu.org/g:17b368b4b4524ce9d11bf79ce7f58d6825156ce0
commit r15-1605-g17b368b4b4524ce9d11bf79ce7f58d6825156ce0
Author: YunQiang Su
Date: Thu Jun 20 01:20:36 2024 +0800
MIPS: Implement vcond_mask optabs for MSA
Currently, we have `mips_expand_vec_cond_expr`, which
YunQiang Su 于2024年6月14日周五 20:12写道：
>
> PR 115416
>
> When we build a cross toolchain, while without --with-sysroot,
> target headers are expected in
> ${test_exec_prefix}/${target_noncanonical}/sys-include
> while it is true only with --with-headers option is used. In ot
> >
> > And FAOD I think a stub check has to remain even after the removal and
> > just cause `configure' to bail out if an unsupported obsolete version of
> > GAS has been identified.
> >
Ohh, I think that we shouldn't remove it now, as I have figure out
the PCREL patch,
and I am still waiting
Maciej W. Rozycki 于2024年6月21日周五 22:00写道：
>
> On Fri, 21 Jun 2024, Maciej W. Rozycki wrote:
>
> > > Yeah, agreed FWIW. This was necessary while the feature was relatively
> > > new, and while we still supported IRIX as, but I can't see any reasonable
> > > justification for using such an ancient
Maciej W. Rozycki 于2024年6月21日周五 20:55写道：
>
> On Fri, 21 Jun 2024, Richard Sandiford wrote:
>
> > > We check gcc_cv_as_mips_explicit_relocs if
> > > gcc_cv_as_mips_explicit_relocs_pcrel
> > > only, while gcc_cv_as_mips_explicit_relocs is used by later code.
> > >
> > > Maybe, it is time for use
https://gcc.gnu.org/g:a16f47f5f34d08b13ee58ea362027c6a479eb82f
commit r14-10336-ga16f47f5f34d08b13ee58ea362027c6a479eb82f
Author: YunQiang Su
Date: Thu Jun 20 10:37:39 2024 +0800
Build: Set gcc_cv_as_mips_explicit_relocs if
gcc_cv_as_mips_explicit_relocs_pcrel
We check
https://gcc.gnu.org/g:573f11ec34eeb6a6c3bd3d7619738f927236727b
commit r15-1506-g573f11ec34eeb6a6c3bd3d7619738f927236727b
Author: YunQiang Su
Date: Thu Jun 20 10:37:39 2024 +0800
Build: Set gcc_cv_as_mips_explicit_relocs if
gcc_cv_as_mips_explicit_relocs_pcrel
We check
https://gcc.gnu.org/g:7b67ec4b50ae523a1e1be410644abb627daa9590
commit r15-1505-g7b67ec4b50ae523a1e1be410644abb627daa9590
Author: YunQiang Su
Date: Tue Jun 18 17:03:51 2024 +0800
MIPS: Set condmove cost to SET(REG, REG)
On most uarch, the cost condmove is same as other noraml
>
> Then GCC emits the wrong trap instruction, wherever it comes from and
> whatever has caused it. The correct ones for integer division by zero
Thanks so much. It is not the bug of Linux kernel or GCC.
It is a bug of me ;) and qemu.
Qemu didn't pass the code of TEQ correctly; and I haven't
The DIV instructions of MIPS won't be trapped themself if the divisor
is zero. The compiler will emit a conditional trap instruct for it.
So the signal will be SIGTRAP instead of SIGFPE.
gcc/testsuite
* c-c++-common/ubsan/overflow-div-3.c: Use SIGTRAP for MIPS.
---
YunQiang Su 于2024年6月20日周四 11:20写道：
>
> Maciej W. Rozycki 于2024年6月20日周四 01:24写道：
> >
> > On Wed, 19 Jun 2024, YunQiang Su wrote:
> >
> > > MIPSr6 removes condition trap instructions with imm, so the instruction
> > > like `teq $2,imm` will be conve
MIPSr6 removes condition trap instructions with imm, so the instruction
like `teq $2,imm` will be converted to
li $at, imm
teq $2, $at
The current version of Gas cannot detect if imm is zero, and output
teq $2, $0
Let's do it in GCC.
gcc
* config/mips/mips.md(conditional_trap_reg):
Maciej W. Rozycki 于2024年6月20日周四 01:24写道：
>
> On Wed, 19 Jun 2024, YunQiang Su wrote:
>
> > MIPSr6 removes condition trap instructions with imm, so the instruction
> > like `teq $2,imm` will be converted to
> > li $at, imm
> > teq $2, $at
> >
> > Th
Collin Funk 于2024年6月20日周四 07:40写道：
>
> I've just fixed the quotes and that typo in one patch. I hope you don't
> mind. When using Autoconf 2.69 and Automake 1.15.1 that copyright diff
> goes away. I'm not familiar with the gcc-autoregen bot but I think this
> should make it happy.
>
> -- >8 --
https://gcc.gnu.org/g:bea447a2982f3094aa3423b5045cea929f4f4700
commit r15-1466-gbea447a2982f3094aa3423b5045cea929f4f4700
Author: Collin Funk
Date: Wed Jun 19 16:36:50 2024 -0700
build: Fix missing variable quotes and typo
When dlopen and pthread_create are in libc the variable is
We check gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel
only, while gcc_cv_as_mips_explicit_relocs is used by later code.
Maybe, it is time for use to set gcc_cv_as_mips_explicit_relocs always now,
as it has been in Binutils for more than 20 years.
gcc
*
Thanks. Sorry for the noise. I have reverted
8088374a868aacab4dff208ec3e3fde790a1d9a3
c6a9ab8c920f297c4efd289182aef9fbc73f5906
I will submit and back port the modification of gcc_cv_as_mips_explicit_relocs
separately.
@Collin Funk Can you sent a new correct/full patch?
https://gcc.gnu.org/g:6d6587bc37f2039225e4fba9acaf7b26e600e3d3
commit r15-1459-g6d6587bc37f2039225e4fba9acaf7b26e600e3d3
Author: YunQiang Su
Date: Thu Jun 20 07:02:47 2024 +0800
Revert "build: Fix missing variable quotes"
This reve
https://gcc.gnu.org/g:a334189739e13f8de1f9af99f8d16970435cebc4
commit r15-1458-ga334189739e13f8de1f9af99f8d16970435cebc4
Author: YunQiang Su
Date: Thu Jun 20 07:02:33 2024 +0800
Revert "Build: Fix typo ac_cv_search_pthread_crate"
This reve
Currently, we have `mips_expand_vec_cond_expr`, which calculate
cmp_res first. We can just add a new extra argument to ask it
to use operands[3] as cmp_res instead of calculating from operands[4]
and operands[5].
gcc
* config/mips/mips.cc(mips_expand_vec_cond_expr): Add extra
MIPSr6 removes condition trap instructions with imm, so the instruction
like `teq $2,imm` will be converted to
li $at, imm
teq $2, $at
The current version of Gas cannot detect if imm is zero, and output
teq $2, $0
Let's do it in GCC.
gcc
*
https://gcc.gnu.org/g:8088374a868aacab4dff208ec3e3fde790a1d9a3
commit r15-1446-g8088374a868aacab4dff208ec3e3fde790a1d9a3
Author: YunQiang Su
Date: Wed Jun 19 22:30:22 2024 +0800
Build: Fix typo ac_cv_search_pthread_crate
The correct variable name
https://gcc.gnu.org/g:c6a9ab8c920f297c4efd289182aef9fbc73f5906
commit r15-1436-gc6a9ab8c920f297c4efd289182aef9fbc73f5906
Author: Collin Funk
Date: Thu Jun 13 17:53:55 2024 -0700
build: Fix missing variable quotes
When dlopen and pthread_create are in libc the variable is
set
On most uarch, the cost condmove is same as other noraml integer,
and it should be COSTS_N_INSNS(1).
In GCC12 or previous, the condmove is always enabled, and from
GCC13, we start to compare the cost.
The generic rtx_cost give the result of COSTS_N_INSN(2).
Let's define it to COSTS_N_INSN(1) in
OK for trunk?
--
YunQiang Su
PR target/111376.
Currently, we are using LUI/ANDI/BEQZ for on-bit-test if the bitpos>=16,
while in fact we can use SLL/BGEZ.
Note:
1) if bitpos<16, we can use ANDI/BEQZ.
2) For R2+, we have EXT.
Known problems:
1. On some uarch, SLL has more delay, such as 74K:
See the talk in
Richard Biener 于2024年6月6日周四 14:20写道：
>
> On Thu, 6 Jun 2024, YunQiang Su wrote:
>
> > Richard Biener 于2024年5月28日周二 17:47写道：
> > >
> > > The following avoids accounting single-lane SLP to the discovery
> > > limit. As the two testcases show this make
Xi Ruoyao 于2024年6月9日周日 21:50写道：
>
> A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and
> pair, and twice fast as a srli/slli pair. When the src reg and the dst
Just want to know that why not adjust the RTX cost of bstrins vs srli/slli?
It may benefit more cases.
> reg
PR 115416
When we build a cross toolchain, while without --with-sysroot,
target headers are expected in
${test_exec_prefix}/${target_noncanonical}/sys-include
while it is true only with --with-headers option is used. In other
cases, the path should be
Sam James 于2024年6月14日周五 09:02写道：
>
> Collin Funk writes:
>
> > When dlopen and pthread_create are in libc the variable is
> > set to "none required", therefore running configure will show
> > the following errors:
> >
> > ./configure: line 8997: test: too many arguments
> > ./configure: line
https://gcc.gnu.org/g:f10896c8e5fe34e51ea61aaa4d4aaedb4677ff13
commit r15-1231-gf10896c8e5fe34e51ea61aaa4d4aaedb4677ff13
Author: YunQiang Su
Date: Mon Jun 10 14:31:12 2024 +0800
MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5
Currently, the default tune
https://gcc.gnu.org/g:e3e5fd0c24c9b82d824da27bf8455bb3654e8eff
commit r15-1230-ge3e5fd0c24c9b82d824da27bf8455bb3654e8eff
Author: YunQiang Su
Date: Sat Jun 8 11:31:19 2024 +0800
MIPS: Use signaling fcmp instructions for LT/LE/LTGT
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt
Richard Sandiford 于2024年6月6日周四 17:54写道：
>
> YunQiang Su writes:
> > YunQiang Su 于2024年5月29日周三 10:02写道：
> >>
> >> Richard Sandiford 于2024年5月29日周三 05:28写道：
> >> >
> >> > YunQiang Su writes:
> >> > > If `find_a_progra
https://gcc.gnu.org/g:8e2eb6039d183b7c571da9eb83b933021c5b29be
commit r15-1127-g8e2eb6039d183b7c571da9eb83b933021c5b29be
Author: YunQiang Su
Date: Sat Jun 8 16:05:13 2024 +0800
MIPS/testsuite: add -mno-branch-likely to r10k-cache-barrier-13.c
In mips.cc(mips_reorg_process_insns
WAYS)
MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
Here PROCESSOR_4KC and PROCESSOR_5KC are both FPU-less.
> Jeff
>
--
YunQiang Su
YunQiang Su 于2024年6月9日周日 18:25写道：
>
> > >
> > > gcc/ChangeLog:
> > >
> > > * ifcvt.cc (cond_move_process_if_block):
> > > Consider the result of targetm.noce_conversion_profitable_p()
> > > when replacing the origin
he trunk.
>
Sorry for the delay report. With this patch the test
gcc.target/mips/movcc-3.c fails.
> Jeff
--
YunQiang Su
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
c.lt.fmt will signal for all NaN, including qNaN;
cmp.lt.fmt will only signal sNaN, while not qNaN;
cmp.slt.fmt has the same semantic as c.lt.fmt;
lt/le of RTL will signaling qNaN.
while in
In mips.cc(mips_reorg_process_insns), there is this claim:
Also delete cache barriers if the last instruction
was an annulled branch. INSN will not be speculatively
executed.
And with -O1 on mips64, we can generate binary code like this,
which fails this test.
gcc/testsuite
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
c.lt.fmt will signal for all NaN, including qNaN;
cmp.lt.fmt will only signal sNaN, while not qNaN;
cmp.slt.fmt has the same semantic as c.lt.fmt;
lt/le of RTL will signaling qNaN.
while in
https://gcc.gnu.org/g:edd90d6d298f006e2c2e6c710ab97cd5ad733cb5
commit r15-1051-gedd90d6d298f006e2c2e6c710ab97cd5ad733cb5
Author: YunQiang Su
Date: Thu Jun 6 12:28:31 2024 +0800
MIPS: Need COSTS_N_INSNS in mips_insn_cost
In mips_insn_cost, COSTS_N_INSNS is missing when we return
From: YunQiang Su
In mips_insn_cost, COSTS_N_INSNS is missing when we return the cost
if count * ratio > 0.
gcc
* config/mips/mips.cc(mips_insn_cost): Add missing COSTS_N_INSNS
to count.
---
gcc/config/mips/mips.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
t; + SLP_TREE_SCALAR_STMTS (res) = vNULL;
> + SLP_TREE_DEF_TYPE (res) = vect_uninitialized_def;
> + res->failed = XNEWVEC (bool, group_size);
> + memset (res->failed, 0, sizeof (bool) * group_size);
> + memset (matches, 0, sizeof (bool) * group_size);
> + return NULL;
> + }
> + --*limit;
> }
> - --*limit;
>
>if (dump_enabled_p ())
> dump_printf_loc (MSG_NOTE, vect_location,
> --
> 2.35.3
--
YunQiang Su
YunQiang Su 于2024年5月29日周三 10:02写道：
>
> Richard Sandiford 于2024年5月29日周三 05:28写道：
> >
> > YunQiang Su writes:
> > > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > > toolchain,
> > > the final fallback is `as/ld` of system.
Richard Sandiford 于2024年6月5日周三 23:20写道：
>
> YunQiang Su writes:
> > Richard Sandiford 于2024年6月5日周三 22:14写道：
> >>
> >> YunQiang Su writes:
> >> > PR target/113179.
> >> >
> >> > In `store_bit_field_using_insv`, we j
Richard Sandiford 于2024年6月5日周三 22:14写道：
>
> YunQiang Su writes:
> > PR target/113179.
> >
> > In `store_bit_field_using_insv`, we just use SUBREG if value_mode
> >>= op_mode, while in some ports, a sign_extend will be needed,
> > such as MIPS64:
> >
Kewen Lin 于2024年6月3日周一 11:03写道：
>
> This is to add new port specific hook implementation
> mips_c_mode_for_floating_type, remove macros FLOAT_TYPE_SIZE
> and DOUBLE_TYPE_SIZE, rename LONG_DOUBLE_TYPE_SIZE to
> MIPS_LONG_DOUBLE_TYPE_SIZE since we poison LONG_DOUBLE_TYPE_SIZE
> but some subtarget
https://gcc.gnu.org/g:1bc4a777b21ae36b116e1842b7c482340ec929ef
commit r11-11457-g1bc4a777b21ae36b116e1842b7c482340ec929ef
Author: YunQiang Su
Date: Wed May 29 02:28:25 2024 +0800
MIPS16: Mark $2/$3 as clobbered if GP is used
PR Target/84790.
The gp init sequence
https://gcc.gnu.org/g:3be8fa7b19d218ca5812d71801e3e83ee2260ea0
commit r13-8809-g3be8fa7b19d218ca5812d71801e3e83ee2260ea0
Author: YunQiang Su
Date: Wed May 29 02:28:25 2024 +0800
MIPS16: Mark $2/$3 as clobbered if GP is used
PR Target/84790.
The gp init sequence
li
https://gcc.gnu.org/g:e26f16424f6279662efb210bc87c77148e956fed
commit r12-10480-ge26f16424f6279662efb210bc87c77148e956fed
Author: YunQiang Su
Date: Wed May 29 02:28:25 2024 +0800
MIPS16: Mark $2/$3 as clobbered if GP is used
PR Target/84790.
The gp init sequence
https://gcc.gnu.org/g:201cfa725587d13867b4dc25955434ebe90aff7b
commit r14-10260-g201cfa725587d13867b4dc25955434ebe90aff7b
Author: YunQiang Su
Date: Wed May 29 02:28:25 2024 +0800
MIPS16: Mark $2/$3 as clobbered if GP is used
PR Target/84790.
The gp init sequence
https://gcc.gnu.org/g:915440eed21de367cb41857afb5273aff5bcb737
commit r15-911-g915440eed21de367cb41857afb5273aff5bcb737
Author: YunQiang Su
Date: Wed May 29 02:28:25 2024 +0800
MIPS16: Mark $2/$3 as clobbered if GP is used
PR Target/84790.
The gp init sequence
li
https://gcc.gnu.org/g:9a92e5e56a7f2b19928b8cb7634f59d9c7b2b582
commit r15-910-g9a92e5e56a7f2b19928b8cb7634f59d9c7b2b582
Author: YunQiang Su
Date: Tue May 28 23:44:49 2024 +0800
MIPS/testsuite: Fix bseli.b fail in msa-builtins.c
commit 05daf617ea22e1d818295ed2d037456937e23530
Richard Sandiford 于2024年5月29日周三 05:28写道：
>
> YunQiang Su writes:
> > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try with
> > -as/ld/objcopy before fa
YunQiang Su 于2024年5月22日周三 17:54写道：
>
> If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
> the final fallback is `as/ld` of system. In fact, we can have a try with
> -as/ld/objcopy before fallback to native as/ld/objcopy.
>
> This patch is derivat
PR Target/84790.
The gp init sequence
li $2,%hi(_gp_disp)
addiu $3,$pc,%lo(_gp_disp)
sll $2,16
addu$2,$3
is generated directly in `mips_output_function_prologue`, and does
not appear in the RTL.
So the IRA/IPA passes are not aware that $2/$3 have
commit 05daf617ea22e1d818295ed2d037456937e23530
Author: Jeff Law
Date: Sat May 25 12:39:05 2024 -0600
[committed] [v2] More logical op simplifications in simplify-rtx.cc
does some simplifications, and then `bseli.b $w1,$w0,255` is found that
it is same with `or.v $w1,$w0,$w1`. So there
When looking for as/ld/objcopy, `find_a_program/file_at_path` only
try to find the raw name, but won't find the one with -
prefix.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(for_each_path): Add more space for -.
(file_at_path):
If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try with
-as/ld/objcopy before fallback to native as/ld/objcopy.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
Jakub Jelinek 于2024年5月22日周三 17:33写道：
>
> On Wed, May 22, 2024 at 05:23:33PM +0800, YunQiang Su wrote:
> > Jakub Jelinek 于2024年5月22日周三 17:14写道：
> > >
> > > On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > > > --- gcc/gcc.cc
Jakub Jelinek 于2024年5月22日周三 17:14写道：
>
> On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > --- gcc/gcc.cc.jj 2024-02-09 14:54:09.141489744 +0100
> > > +++ gcc/gcc.cc 2024-02-09 22:04:37.655678742 +0100
> > > @@ -2410,8 +2410,7 @@ read_sp
pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "o");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "o");
> break;
>
> case 's':
> @@ -1599,8 +1634,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_UNSIGNED,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "u");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "u");
> break;
>
> case 'f':
> @@ -1629,8 +1664,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_HEX,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "x");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "x");
> break;
>
> case '.':
> @@ -2774,6 +2809,18 @@ test_pp_format ()
>ASSERT_PP_FORMAT_2 ("17 12345678", "%wo %x", (HOST_WIDE_INT)15,
> 0x12345678);
>ASSERT_PP_FORMAT_2 ("0xcafebabe 12345678", "%wx %x",
> (HOST_WIDE_INT)0xcafebabe,
> 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%zd %x", (ssize_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%zi %x", (ssize_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%zu %x", (size_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%zo %x", (size_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("cafebabe 12345678", "%zx %x", (size_t)0xcafebabe,
> + 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%td %x", (ptrdiff_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%ti %x", (ptrdiff_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%tu %x", (ptrdiff_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%to %x", (ptrdiff_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("1afebabe 12345678", "%tx %x", (ptrdiff_t)0x1afebabe,
> + 0x12345678);
>ASSERT_PP_FORMAT_2 ("1.00 12345678", "%f %x", 1.0, 0x12345678);
>ASSERT_PP_FORMAT_2 ("A 12345678", "%c %x", 'A', 0x12345678);
>ASSERT_PP_FORMAT_2 ("hello world 12345678", "%s %x", "hello world",
>
> Jakub
>
--
YunQiang Su
Andrew Pinski 于2024年5月21日周二 20:23写道：
>
> On Tue, May 21, 2024 at 5:12 AM YunQiang Su wrote:
> >
> > If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try
> > with -as/ld b
If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try
with -as/ld before fallback to native as/ld.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(execute):
https://gcc.gnu.org/g:d3b4ba120ce3b743838c3545a24554989955722a
commit r15-659-gd3b4ba120ce3b743838c3545a24554989955722a
Author: YunQiang Su
Date: Thu May 16 02:30:50 2024 +0800
MIPS: Remove -m(no-)lra option
PR target/113955
The `-mlra` option was introduced in 2014 for MIPS
PR target/113955
The `-mlra` option was introduced in 2014 for MIPS, and was set to
default since then. It's time for us to drop no-lra support by
dropping -m(no-)lra options.
gcc:
* config/mips/mips.cc(mips_option_override):
Drop mips_lra_flag variable;
(mips_lra_p):
https://gcc.gnu.org/g:0c6dd4b0973738ce43e76b468a002ab5eb58aaf4
commit r15-393-g0c6dd4b0973738ce43e76b468a002ab5eb58aaf4
Author: YunQiang Su
Date: Mon May 13 14:15:38 2024 +0800
Revert "MIPS: Support constraint 'w' for MSA instruction"
This reve
https://gcc.gnu.org/g:9ba01240864ac446052d97692e2199539b7c76d8
commit r15-339-g9ba01240864ac446052d97692e2199539b7c76d8
Author: YunQiang Su
Date: Wed May 8 19:04:33 2024 +0800
MIPS: Support constraint 'w' for MSA instruction
Support syntax like:
asm volatile ("fm
Support syntax like:
asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));
gcc
* config/mips/constraints.md: Add new constraint 'w'.
gcc/testsuite
* gcc.target/mips/msa-inline-asm.c: New test.
---
gcc/config/mips/constraints.md | 3 +++
https://gcc.gnu.org/g:7d5d2b879ae7636ca118fb4f3a08b22705cdeacb
commit r15-171-g7d5d2b879ae7636ca118fb4f3a08b22705cdeacb
Author: YunQiang Su
Date: Mon Apr 29 00:33:44 2024 +0800
expmed: TRUNCATE value1 if needed in store_bit_field_using_insv
PR target/113179
https://gcc.gnu.org/g:70d30dd656957f518b8169a125f6b17f53da8237
commit r15-170-g70d30dd656957f518b8169a125f6b17f53da8237
Author: YunQiang Su
Date: Sun May 5 23:12:37 2024 +0800
config-ml.in: Fix multi-os-dir search
When building multilib libraries, CC/CXX etc are set
https://gcc.gnu.org/g:11c13111ac64a035d6c4ea6c118eff4ece7a9d9b
commit r15-43-g11c13111ac64a035d6c4ea6c118eff4ece7a9d9b
Author: Jie Mei
Date: Sun Apr 28 16:57:31 2024 +0800
MIPS: Add MIN/MAX.fmt instructions support for MIPS R6
This patch adds the smin/smax RTL mode for the
I will apply this patch.
While we still have a problem about
```
float max(float a, float b) { return a>=b?a:b; }
```
If it is compiled with `-ffinite-math-only -fsigned-zeros -O2
-mips32r6 -mabi=32`,
`max.s` can be used.
The max.fmt/min.fmt of MIPSr6 can process +0/-0 correctly.
Xi Ruoyao 于2024年3月26日周二 18:10写道：
>
> On Tue, 2024-03-26 at 11:15 +0800, YunQiang Su wrote:
>
> /* snip */
>
> > With -ffinite-math-only -fno-signed-zeros, it does work with
> > x >= y ? x : y
> > while without `-ffinite-math-only -fno-signed-zeros`, it c
Jeff Law 于2024年1月3日周三 01:00写道：
>
>
>
> On 1/1/24 09:48, YunQiang Su wrote:
> > When building multilib libraries, CC/CXX etc are set with an option
> > -B*/lib/, instead of -B/lib/.
> > This will make some trouble in some case, for example building
> > cro
PR target/113179.
In `store_bit_field_using_insv`, we just use SUBREG if value_mode
>= op_mode, while in some ports, a sign_extend will be needed,
such as MIPS64:
If either GPR rs or GPR rt does not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is
Xi Ruoyao 于2024年3月20日周三 15:12写道：
>
> We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
> arguments and there is nothing to advance, but that is not the case
> for (...) functions returning by hidden reference which have one such
> artificial argument. This is causing
Jie Mei 于2024年3月25日周一 17:46写道：
>
> This patch adds the smin/smax RTL mode for the
> min/max.fmt instructions.
>
> Also, since the min/max.fmt instrucions applies to the
> IEEE 754-2008 "minNum" and "maxNum" operations, this
> patch also provides the new "fmin3" and
> "fmax3" modes.
>
>
https://gcc.gnu.org/g:bb819067b3037dbc847aef6c46b8dc6cd5b50962
commit r14-9661-gbb819067b3037dbc847aef6c46b8dc6cd5b50962
Author: YunQiang Su
Date: Wed Mar 20 16:25:04 2024 +0800
MIPS: Predefine __mips_strict_alignment if STRICT_ALIGNMENT
Arm32 predefines __ARM_FEATURE_UNALIGNED
Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid.
Let's define __mips_strict_alignment for MIPSr6 and -mstrict-align
is used.
Not that, this macro is always defined for pre-R6.
gcc
config/mips/mips.h
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