Thank you all very much for your comments and advice!
It certainly has helped me to gain a better perspective on porting GCC
to a new architecture.
It's not directly a suggestion from my Betreuer; a few suggested it
as a Praktikum or as a masters thesis, and I wanted to look into it and
see
On 02/05/12 16:36, Ian Lance Taylor wrote:
I don't know what a bachelor thesis is, so I don't know if this would be
suitable. A GCC port by itself would be too simple for a masters thesis
in the U.S.
Yes, on second thought, the Betreuer I mentioned did not say anything
about a masters
Hello,
In a course at my university (Universität Würzburg, Germany) we have
created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
if we want to do anything with it, we have to write the assembly code
On Wed, May 02, 2012 at 01:30:19PM +0200, Ben Morgan wrote:
In a course at my university (Universität Würzburg, Germany) we have
created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
if we want to do
On Wed, 2 May 2012, Ben Morgan wrote:
Hello,
In a course at my university (Universität Würzburg, Germany) we have
created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
if we want to do anything with
Ben Morgan wrote:
In a course at my university (Universität Würzburg, Germany) we have created
a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL) which we then
play onto a FPGA (the Xilinx Spartan-3AN) to use. So far if we want to do
anything with it, we have to write the assembly
Ben Morgan benm.mor...@gmail.com writes:
In a course at my university (Universität Würzburg, Germany) we have
created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
if we want to do anything with it, we
Ben Morgan wrote:
In a course at my university (Universität Würzburg, Germany) we have created
a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL) which we then
play onto a FPGA (the Xilinx Spartan-3AN) to use. So far if we want to do
anything with it, we have to write the
On Wed, 2 May 2012, Ian Lance Taylor wrote:
It's worth looking at Anthony Green's blog about implementing moxie at
http://moxielogic.org/ , as he described the process of doing a full GCC
port.
Let me clarify that Anthony described porting in his GGX patch archives,
linked in my other
