i am studing RTL that is gcc front-end
insn RTX has seven elements
ex) (insn id prev next pattern code log_links reg_notes)
(insn 12 10 14 (set (reg:QI 12 A0) (reg:QI 1 R1) -1 (nil) (nil))
where i get the impormation about code, log_links,
reg_notes
Dear All,
The GCC source reference 4.8.1 will synthesized some of the double
word operations(SI mode) like add /sub in the below case from the word
size (HI) patterns,
(code snippet)
expand_binop_directly function in the optabs.c.
/* These can be done a word at a time by propagating carries. */
hi,
I'm trying to understand the rtl genrated by gcc for mips processor.I
have read gcc internals by Richard Stallman but there are still some
confusions in the rtl language.
Following is a snippet of code which i'm trying to understand.
(insn 9 6 10 (nil) (set (reg:SI 182)
Hi,
I have noticed that the INSN_CODE for all patterns in the rtl dumps
.00.expand are -1 ... does this mean that the .md file was not used for the
initial RTL generation?
best regards
Andrija Radicevic
Hi all,
RTL represents a low-level language, machine-independent. But I didn't
find any especification of such language represented. This is, I found
no document where the language represented were described or defined
in a grammar way. So, I 'd thank you to show me where the RTL-la
하태준 wrote:
> where i get the impormation about code, log_links, reg_notes
See the internals documentation, in the file gcc/doc/rtl.texi, or on the
web at
http://gcc.gnu.org/onlinedocs/gccint/Insns.html#Insns
See also the sources for more info, as the docs may not be fully up to
date, in partic
Can someone tell me if there is a way to generate RTL code which does not
include use and def of the same pseudo in the same insn? Of course, I
can break every such instruction into two but I am wondering if it is
already
there or anyone has the code already available.
i.e. generate
t=p56+p76
Do we currently have an RTL infix printing mechanism hidden away
somewhere? I seem to vaguely recall new-ra might have had something
once upon a time... I also suspect others have fooled with it over the
years.
Is there code laying around I can snarf and work with?
Andrew
On 03/25/14 06:23, Umesh Kalappa wrote:
Dear All,
The GCC source reference 4.8.1 will synthesized some of the double
word operations(SI mode) like add /sub in the below case from the word
size (HI) patterns,
(code snippet)
expand_binop_directly function in the optabs.c.
/* These can be done a
Am 03/25/2014 01:28 PM, schrieb Jeff Law:
On 03/25/14 06:23, Umesh Kalappa wrote:
Dear All,
The GCC source reference 4.8.1 will synthesized some of the double
word operations(SI mode) like add /sub in the below case from the word
size (HI) patterns,
(code snippet)
expand_binop_directly functi
Georg,
Currently we implemented the expander ,where passing arguments and
handling return type had been taken care in the expander along the
emitting call insn.
Do you have any suggestion over here like other practical approach ?
Appreciate your reply here.
Thank you in advance
~Umesh
On W
Greetings All,
After getting it some thought I've yet to see any real focus on making the RTL
layers or just the architectural backends parallel in nature. Is there a reason
for this as my assumption is that after reading parts of the x86 and rs6000
backend code it's not needed.
Thi
Hi,
I'm trying to make a gcc backend for a stack machine, is there a way to
disable register specific behaviour required by target.h, target.c? also
all preserved names in the RTL language assume usages of operands (addm3
mulm3 etc) which is not an option in my target, do I have to manually s
On 6/7/06, kernel coder <[EMAIL PROTECTED]> wrote:
hi,
I'm trying to understand the rtl genrated by gcc for mips processor.I
have read gcc internals by Richard Stallman
His name may be on it, but it's actually supposed to be maintained by
the gcc team.
I say "supposed&qu
> kernel coder writes:
kernel> In the above code following part is still unclear to me
kernel> [0 a+0 S4 A32]
The values in order represent:
Alias Set
Offset from a base expression, if part of a larger object
Size
Alignment
David
hello all,
Sorry i am asking this kind of question.This might be weird to most of you but
i am new to GCC.
Can somebody tell me how to analyze the below instruction pattern
(insn 8 6 9 1 (parallel [
(set (reg/f:SI 32)
(symbol_ref:SI ("t") ))
(clobber (reg:
ons
in the instructions link list;
1 is the serial number of the instruction basic block.
You can read more about the RTL representation of insn in
http://gcc.gnu.org/onlinedocs/gccint/Insns.html.
Also, the following are taken from http://gcc.gnu.org/onlinedocs/gccint/:
clobber indicates something is cl
Hi all,
I need some clarification in understanding the below mentioned RTL Expressions
1. (insn 11 10 12 0
gcc/testsuite/gcc.c-torture/execute/20020611-1.c:13 (parallel [
(set (reg/f:SI 13 a5 [28])
(symbol_ref:SI ("n") [flags 0x2] ))
(clobber (re
Hello all,
While going through the RTL dumps, I noticed a few things which i need
to get clarified.
Below is the extract, in which i get the doubt.
(insn 106 36 107 6 (set (reg:SI 13 a5)
(const_int -20 [0xffec])) 17 {movsi_short_const} (nil)
(nil))
(insn 107 106 108 6 (parallel
Hi all,
Can any one get me the information/implementation of below mentioned
functions?
1. operands[0] = gen_rtx_REG (SImode,REGNO (set_dest));
2. operands[0] = gen_highpart (SImode, set_dest);
Are both functionalities similiar if i use the above functions to get
the 32 bit word from a 64 bit
On 12/1/06, Andrija Radicevic <[EMAIL PROTECTED]> wrote:
Hi,
I have noticed that the INSN_CODE for all patterns in the rtl dumps
.00.expand are -1 ... does this mean that the .md file was not used for the
initial RTL generation?
It was used, but it is assumed that the initial RTL produ
I want to start a discussion about some possible changes to the RTL
level of GCC.
This discussion is motivated by some of the issues raised in bug
26854. We have addressed many of the issues in this bug, but the
remaining issue is cost, in both time and space, for the UD and DU
chains built by
Hi Fran,
> I have read the documentation and i didn't found where it is
> described, maybe I searched in wrong place.
RTL language definition is in rtl.def and gives the different
operators and operands. info gccint on a standard linux distribution
should help you figure out detail
Fran Baena wrote:
RTL represents a low-level language, machine-independent. But I didn't
find any especification of such language represented. This is, I found
no document where the language represented were described or defined
in a grammar way.
RTL isn't a programming language, and
Hi Ramana,
> > I have read the documentation and i didn't found where it is
> > described, maybe I searched in wrong place.
>
>
> RTL language definition is in rtl.def and gives the different
> operators and operands. info gccint on a standard linux distribution
2008/3/10, Jim Wilson <[EMAIL PROTECTED]>:
> Fran Baena wrote:
> > RTL represents a low-level language, machine-independent. But I didn't
> > find any especification of such language represented. This is, I found
> > no document where the language represented wer
"Fran Baena" <[EMAIL PROTECTED]> writes:
> 2008/3/10, Jim Wilson <[EMAIL PROTECTED]>:
>> Fran Baena wrote:
>> > RTL represents a low-level language, machine-independent. But I didn't
>> > find any especification of such language represented.
Hi,
> By the way, RTL is not really machine-independent. The data
> structures are machine independent. But the contents are not. You
> can not, even in principle, take the RTL generated for one processor
> and compile it on another processor.
I thought that RTL represent
"Fran Baena" <[EMAIL PROTECTED]> writes:
>> By the way, RTL is not really machine-independent. The data
>> structures are machine independent. But the contents are not. You
>> can not, even in principle, take the RTL generated for one processor
>> an
> I thought that RTL represented something close to the target machine,
> but not machine-dependent. I firstly thought that the output of the
> middle-end was an RTL machine-independent representation, to which is
> applied a few low-optimization machine-independent passes, and aft
Hello all,
Maybe I can add a few comments here. This is the way I see the RTL
within GCC. Details are at:
http://www.cfdvs.iitb.ac.in/~amv/gcc-int-docs/
and in particular, I'd like to point to
http://www.cfdvs.iitb.ac.in/~amv/gcc-int-docs/html/gcc-conceptual-structure.html.
(BTW, comm
Hi everybody,
Im interested whether there is gcc support (at the RTL
level) after unrolling which allows to disambiguate
memory accesses present in RTL constructs (specially
among memory accesses generated due to unrolling) for
machines that do not support indexed addressing modes.
I am aware
gen_rtx_SET. I could
insert inline assembly with the ASM_OPERANDS macro, but I really want to do this
with pure RTL. Essentially, I just want to emit: "and %eax, $0x7"
Once I emit my rtx into the list of insns, GCC gives me an "unrecognized insn"
error. I can trace the code th
Rajkishore Barik wrote:
Can someone tell me if there is a way to generate RTL code which does not
include use and def of the same pseudo in the same insn?
That depends on how you are generating RTL, but it should be pretty
obvious that you can use gen_reg_rtx to generate a temp reg for use as a
On Fri, May 13, 2005 at 02:31:12PM -0400, Andrew MacLeod wrote:
> Is there code laying around I can snarf and work with?
See sched-vis.c.
r~
On Fri, 2005-05-13 at 14:31 -0400, Andrew MacLeod wrote:
> Do we currently have an RTL infix printing mechanism hidden away
> somewhere? I seem to vaguely recall new-ra might have had something
> once upon a time... I also suspect others have fooled with it over the
> years.
Yes
Hi:
Yeah. You are right. Here is another RTL unrecognized. It happened
after reload.
(insn 749 156 147 22 (set (reg:HI 5 R5)
(subreg:HI (mem/c:SI (plus:SI (reg/f:SI 15 R15)
(const_int 108 [0x6c])) [19 d0+0 S4 A32]) 0)) -1 (nil))
I traced the lots of functions like
Hi,
I have a problem about RTL sequence.
If I wanna generate the RTL in sequence, and don't let gcc to schedule them.
Like the following(all the variable is rtx):
emit_insn(reg0, operands[0]);
emit_insn(reg1, reg0);
emit_insn(operands[0], reg1);
But gcc will
Hi,
Can anybody explain about the unspec_volatile() rtl template usage, sample
example and the purpose of it.
Thanks and Regards
Raja Saleru
Hi,
Can anyone tell me if there is a way to find out roughly the
source line no of a particular rtl instruction (if there is ) ? I
believe tree has a link to the source line no, in which case how do I
find out the source tree node for a particular rtl stmt ?
I appreciate any ideas
Hi rth,
The stack space sharing you added to cfgexpand.c breaks RTL alias
analysis.
For example, the attached test case breaks for pentiumpro at -O2.
The problem apparently is that the second store to c is moved up
before before the load.
This looks like a serious problem to me...
Many thanks
In gcc/combine.cc
I have written a pattern to emit a complex rtl instruction which uses 'and'
'shift' 'lshiftrt' and 'or' in a single pattern.But pattern not recognised
as single pattern.I changed the cost of this instruction to 0.Still pattern
Hi All,
I'm trying to figure out how to prevent LRA selecting alternatives that
result in values being copied from A to B for one instruction, and then
immediately back from B to A again, when there are apparently more
sensible alternatives available.
I have an insn with the following patter
Hi All,
I am porting gcc for an internal processor and I am having some issues with
math instructions. Our processor uses two operands for math instructions which
are usually of the form OP0 = OP0 + OP1. The RTL pattern (for addm3) in gcc
uses the form OP0 = OP1 + OP2. I understand that
to do an analysis
of a compilation unit or whole program at the level or RTL. From
what we have been able to gleen (note: we're all relative
newcomers to the GCC code base), all RTL transformation and
analysis is done at the level of functions only. Once pass_final
runs, the RTL has been
On 11/15/2017 08:33 AM, Ábrahám Endre wrote:
> Hi,
> I'm trying to make a gcc backend for a stack machine, is there a way to
> disable register specific behaviour required by target.h, target.c? also
> all preserved names in the RTL language assume usages of operands (addm3
>
,
> > I'm trying to make a gcc backend for a stack machine, is there a way to
> > disable register specific behaviour required by target.h, target.c? also
> > all preserved names in the RTL language assume usages of operands (addm3
> > mulm3 etc) which is not an option i
I've found this in the docs, reg-stack.c comments seems like this is what
I'm looking for, RTL needs registers some way and the output is just a
distance from the top of the stack. Hope this will know push/pop implicitly
https://gcc.gnu.org/onlinedocs/gccint/Stack-Registers.html#Stack
Dear Group,
Need a favour from you all ,Im very new to gcc framework such and
learning the same ,
I was looking at the RTL insns sets by dumping the c.144.exapnd dump
file before reload pass for the various target and I do see the
difference in the RTL insns set for two different targets for below
Hi,
Could anybody pls advise, if I can detect that given RTL `call` is
actually a setjmp ()?
I see no references in dump...
(call_insn 6 5 7 (set (reg:SI 0 ax)
(call (mem:QI (symbol_ref:DI ("_setjmp") [flags 0x41]
) [0 _setjmp S1 A8])
(const_int 0 [0])))
hi,
Following is a c code .
int a;
main()
{
a=a+1;
}
This RTL generated for this programe for mips processor is
/***/
; Function main
(note 2 0 3 NOTE_INSN_DELETED)
(note 3 2 4 NOTE_INSN_FUNCTION_BEG)
(note 4 3 5 NOTE_INSN_DELETED)
(note
On Mon, Oct 16, 2006 at 05:20:44AM -0700, Mohamed Shafi wrote:
> hello all,
>
> Sorry i am asking this kind of question.This might be weird to most of you
> but i am new to GCC.
> Can somebody tell me how to analyze the below instruction pattern
>
> (insn 8 6 9 1 (parallel [
> (set (
cc.gnu.org
Sent: Monday, October 16, 2006 7:28:42 PM
Subject: Re: Abt RTL expression
On Mon, Oct 16, 2006 at 05:20:44AM -0700, Mohamed Shafi wrote:
> hello all,
>
> Sorry i am asking this kind of question.This might be weird to most of you
> but i am new to GCC.
> Can somebody te
On Mon, Oct 16, 2006 at 09:32:58PM -0700, Mohamed Shafi wrote:
>
> In th document
> http://gcc.gnu.org/onlinedocs/gccint/Insns.html#Insns
>
> it is said that "An integer that says which pattern in the machine
> description matches
> this insn, or -1 if the matching has not yet been attempted.Su
> It is because matching has not yet been attempted.
ok.. so what is the option to get hold of a rtl dump after all the matching is
done
- Original Message
From: Rask Ingemann Lambertsen <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@gcc.gnu.org
On Tue, Oct 17, 2006 at 01:10:02AM -0700, Mohamed Shafi wrote:
> > It is because matching has not yet been attempted.
>
> ok.. so what is the option to get hold of a rtl dump after all the matching
> is done
-fdump-rtl-vregs, although if you want to see the prologue and ep
> a) To which register is the value of n copied? if a5 is the register
> what is 13 and [28]
All of those numbers refer to the same register -
13 is the number of the register; a5 is the name of the register
(if it is an hard register);
[28] is the number of the old pseudo register.
(please look
Hi all,
This small bit of code worked fine with all optimization except Os.
unsigned int n = 30;
void x ()
{
unsigned int h;
h = n <= 30; // Line 1
if (h)
p = 1;
else
p = 0;
}
when we tried to debug the emitted RTL instruction for Os, it was
found that RTL instruction
Hi all,
I am working with a GCC Cross compiler version 4.1.1.
This small bit of code worked fine with all optimization except Os.
unsigned int n = 30;
void x ()
{
unsigned int h;
h = n <= 30; // Line 1
if (h)
p = 1;
else
p = 0;
}
when we tried to debug the emitted
RTL dump of the corresponding
pass?
3. Any documentation regarding the above?
Regards,
Rohit
Hello all,
Can anyone tell me what the below expression means ?
(insn 38 37 40 4 (parallel [
(asm_operands/v ("") ("") 0 [ //line 2
(reg:SI 32 [ s5.1 ])
//line 3
]
[
(asm_input:SI ("r")
= 0;
}
When we tried to debug the emitted RTL instruction for Os, it was
found that RTL instruction for Line #1 were not at all emitted. i.e.
there is no reference with respect to "h or n" (Instructions 11, 12,
13 are not emitted in life1 pass). For the same optimization Os, if we
use
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> (insn 106 36 107 6 (set (reg:SI 13 a5)
> (const_int -20 [0xffec])) 17 {movsi_short_const} (nil)
> (nil))
>
> (insn 107 106 108 6 (parallel [
> (set (reg:SI 13 a5)
> (plus:SI (reg:SI 13 a5)
>
> Can any one get me the information/implementation of below mentioned
> functions?
>
> 1. operands[0] = gen_rtx_REG (SImode,REGNO (set_dest));
> 2. operands[0] = gen_highpart (SImode, set_dest);
Sure, emit-rtl.c, lines 488 and 1165.
Ben
Hi,
how could I find out from which patterns, in the md file, the 00.expand file
was generated (i.e. to map the patterns in the expand file with the ones in the
.md file)? Is there a compiler option/switch which would tell the compiler mark
the patterns in the expand file with the insns names fr
On Feb 27, 2008, Kenneth Zadeck <[EMAIL PROTECTED]> wrote:
> The appeal for birthpoints is that unlike the abortive attempt in
> the past to add SSA to RTL, adding a noop moves does not really mess
> up anything.
IIRC, when people tried to do RTL SSA, the problem was with match
on community without knowledge of Reif and Lewis, but i
need to check this for sure.
Jeff Law wrote:
> Kenneth Zadeck wrote:
>> jeff,
>>
>> i posted this earlier today to the gcc mailing list. I was wondering
>> what your feelings were on this. I know you had a hand in the
Thanks for the quick response. As it turns out, the libcall issue will
soon be gone, as bonzini will be deleting them. We have finally
overcome that issue.
Not really. There seems always to be something that prevents them from
being deleted, and I have no time to spend on GCC at work righ
D chains is not by chance) without introducing phi functions. phi
> operands would be a birthpoint's reaching defs, in practice, right?
Yes, I do believe that wast majority of DU/UD code can stay as it is.
We just need to introduce the PHI nodes, either in a way Gimple does
that in separat
only interfere with optimizations when the
situation is already horrible. In fact, it wouldn't surprise me if this
could actually *help* a number of passes, including RA, for larger
values of X :-)
Does RTL have an efficient copy prop? That could then naturally remove
these copies when desired
ouldn't surprise me if
> this could actually *help* a number of passes, including RA, for
> larger values of X :-)
>
> Does RTL have an efficient copy prop? That could then naturally remove
> these copies when desired, and then they could be added back in as
> needed the next time
> My real point in starting this discussion was to try to interest
> (sucker) one of the subreg specialists into helping me solve the issue
> of inserting move at the birthpoint where subregs or strict lower values
> are used.
I don't see your problem here. Any use (as in reading) of a
subreg ca
On Thu, Feb 28, 2008 at 2:32 PM, Paolo Bonzini <[EMAIL PROTECTED]> wrote:
>
> > Thanks for the quick response. As it turns out, the libcall issue will
> > soon be gone, as bonzini will be deleting them. We have finally
> > overcome that issue.
>
> Not really. There seems always to be somethi
Steven Bosscher wrote:
> On Thu, Feb 28, 2008 at 2:32 PM, Paolo Bonzini <[EMAIL PROTECTED]> wrote:
>
>> > Thanks for the quick response. As it turns out, the libcall issue will
>> > soon be gone, as bonzini will be deleting them. We have finally
>> > overcome that issue.
>>
>> Not really.
"Steven Bosscher" <[EMAIL PROTECTED]> writes:
> On Thu, Feb 28, 2008 at 2:32 PM, Paolo Bonzini <[EMAIL PROTECTED]> wrote:
> >
> > > Thanks for the quick response. As it turns out, the libcall issue will
> > > soon be gone, as bonzini will be deleting them. We have finally
> > > overcome that
On 28 Feb 2008 12:41:30 -0800, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> libcalls are still used for no-conflict blocks. This may be what you
> mean by the scheduling thing. No-conflict blocks are emitted by
> emit_no_conflict_block and checked in local-alloc.
I thought the no-conflict bl
"Steven Bosscher" <[EMAIL PROTECTED]> writes:
> On 28 Feb 2008 12:41:30 -0800, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> > libcalls are still used for no-conflict blocks. This may be what you
> > mean by the scheduling thing. No-conflict blocks are emitted by
> > emit_no_conflict_block an
On 28 Feb 2008 13:52:56 -0800, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> I think it's probably a blocker issue on 32-bit x86 until we complete
> the lower subreg work to track subreg lifetimes to detect no-conflict
> sections manually. I have an implementation of that written before
> DF,
On 2/28/08 8:32 AM, Paolo Bonzini wrote:
FUD chains are basically SSA without subscripts -- and hence, without
overlapping live ranges.
No, they have subscripts. They just do not have OLRs.
Diego.
On 2/27/08 6:15 PM, Kenneth Zadeck wrote:
Comments? Volunteers?
How about adding FUD chains instead of the dense UD chains we have
today? FUD chains are almost trivial to port from gimple-ssa into RTL.
We already overlay a use-def web on the RTL representation using the new
dataflow bits
On 2/28/08 8:59 AM, Jan Hubicka wrote:
Yes, I do believe that wast majority of DU/UD code can stay as it is.
We just need to introduce the PHI nodes, either in a way Gimple does
that in separate section of CFG or as real RTL noop moves (or we can
even have RTL PHI code that would behave same
e are not going to use a rewriting SSA form, I believe that the
original problems we had with RTL-SSA can be avoided.
Diego.
On Fri, Feb 29, 2008 at 11:51 PM, Diego Novillo <[EMAIL PROTECTED]> wrote:
> If we are not going to use a rewriting SSA form, I believe that the
> original problems we had with RTL-SSA can be avoided.
The nice thing about birth points would be that most RTL optimizers
can look
On 2/29/08 7:04 PM, Steven Bosscher wrote:
I am not sure what would happen if GCC would start using FUD chains.
Is it like in SSA that every register is assigned only once?
But this would only affect the UD chains built by the DF code. My idea
is to build the same UD chains, but make them sp
Diego Novillo wrote:
> On 2/29/08 7:04 PM, Steven Bosscher wrote:
>
>> I am not sure what would happen if GCC would start using FUD chains.
>> Is it like in SSA that every register is assigned only once?
>
> But this would only affect the UD chains built by the DF code. My
> idea is to build the s
On Fri, Feb 29, 2008 at 20:39, Kenneth Zadeck <[EMAIL PROTECTED]> wrote:
> I personally dislike the fact that the middle end keeps the phi's separate.
Six of one, half a dozen of the other. If you put the PHIs in the IL
stream, then you need to be careful about not moving anything before
or in
we are careful to model them
correctly when we see them individually. The question that i have is
when you see a join where one arm modifies the the first byte and the
other arm modifies the 4th byte. there is no store to the second and
third bytes and no way in rtl to exactly model it as a s
> The two complications are:
> 1) libcalls
I am probably dense here, but why we can't just ignore existence of
libcalls for dataflow framework? This exist so we can effectivly remove
blocks of code in dead code removal and do some other changes, but I
don't see how they can be less friendly to F
I nodes on side especially in
FUD chain where rest of your SSA is on side too. But if we go with the
extra instruction scheme, I think you are much better to use RTL USE
instruction. The moves are generated by target machinery and can do
funny things, like clobbering flags or whatever. USEs are trans
tay independent, but that is.
The extra care is the problem. To be fair, the problem is manageable
(see the whole DCE vs. libcall notes thread from last year) but it
adds a lot of complexity and defeats the benefits of having FUD
chains. Basically the same problem as the issues we had for RTL SSA.
S
the benefits of having FUD
I see. This should not get that worse with FUD.
> chains. Basically the same problem as the issues we had for RTL SSA.
> See these threads:
>
> http://gcc.gnu.org/ml/gcc-patches/2000-07/msg01152.html
> http://gcc.gnu.org/ml/gcc-patches/2000-07/msg01174
By the way, I still don't understand how birth points would work. Can
someone give an example of what the insn stream would look like with
birth points, and what the DU/UD chains would look like?
With a big IIUC, and using a high-level IR for simplicity
if (a < 5) goto BB1; else goto BB2;
Diego Novillo wrote:
On 2/29/08 7:04 PM, Steven Bosscher wrote:
I am not sure what would happen if GCC would start using FUD chains.
Is it like in SSA that every register is assigned only once?
But this would only affect the UD chains built by the DF code.
Yes, that's what I meant by "no su
On 3/1/08 8:50 AM, Paolo Bonzini wrote:
Yes, that's what I meant by "no subscripts" (see also my other message
re. birthpoints). Instead of subscripting variables you have multiple
defs for each variable. End each def is obviously assigned only once,
and each use in the IL stream except for
d the
other arm modifies the 4th byte. there is no store to the second and
third bytes and no way in rtl to exactly model it as a single move.
Two options:
- Conservatively treat partial references as full references. So, two
different subreg references with the same parent are considered
refer
On 3/1/08 5:13 AM, Jan Hubicka wrote:
while I am with Diego that would preffer PHI nodes on side especially in
FUD chain where rest of your SSA is on side too. But if we go with the
extra instruction scheme, I think you are much better to use RTL USE
instruction. The moves are generated by
The problems are orthogonal in the sense
that it *can* be done. But I, for one, would not even start working
on RTL-FUD before libcall blocks are dead and gone. Just because I
wouldn't want to handle it as a special case that
Gr.
Steven
ed for the people working on the df branch. They were a major
headache.
You're right technically: The problems are orthogonal in the sense
that it *can* be done. But I, for one, would not even start working
on RTL-FUD before libcall blocks are dead and gone. Just because I
wouldn't wa
On Sat, Mar 1, 2008 at 2:46 PM, Paolo Bonzini <[EMAIL PROTECTED]> wrote:
>
> > By the way, I still don't understand how birth points would work. Can
> > someone give an example of what the insn stream would look like with
> > birth points, and what the DU/UD chains would look like?
>
> With a
f the DF objects are part of the RTL IL.
What about keeping things up-to-date after applying some
transformations? It is already hard to keep UD/DU chains up-to-date
now (I don't think any pass successfully does so right now). This
should be a lot easier if you fully factorize your UD c
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