On Dec 9, 2007 2:19 AM, Thomas Sailer [EMAIL PROTECTED] wrote:
Has anyone faced a similar problem before? Are there targets for which
both VLIW and DBR are enabled? Perhaps ia64?
Ok, this was a long time back, but Yes I have faced a similar problem.
We disabled
delayed branch scheduling and
Hi thomas,
Thanks for your reply. A couple of questions below.
Thomas Sailer wrote:
Has anyone faced a similar problem before? Are there targets for which
both VLIW and DBR are enabled? Perhaps ia64?
I did something similar a few months ago.
What was your target? Is the target code
When do you un-parallel those instructions? And, how?
I don't; I use a C function to output such an insn group.
In that C function, I basically save the global state of final, and use
functions of final.c to output constitutent insns.
The insn group output function basically looks like this:
Hi,
I am trying to enable delayed branch scheduling on our port of Gcc for
picochip (16-bit VLIW DSP). I understand that delayed-branch is run as a
seperate pass after the DFA scheduling is done. We basically depend on
the TImode set on the cycle-start instructions to decide what
instructions
Has anyone faced a similar problem before? Are there targets for which
both VLIW and DBR are enabled? Perhaps ia64?
I did something similar a few months ago.
The problem is that haifa and the delayed branch scheduling passes don't
really fit together. delayed branch scheduling happily undoes
