https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #5 from Peter Cordes ---
> pextrw requires sse4.1 for mem operands.
You're right! I didn't double-check the asm manual for PEXTRW when writing up
the initial report, and had never realized that PINSRW wasn't symmetric with
it.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #4 from Hongtao.liu ---
Fixed in GCC12.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #3 from CVS Commits ---
The master branch has been updated by hongtao Liu :
https://gcc.gnu.org/g:e4352a0fee49441a32d12e8d8b98c425cfed4a86
commit r12-7841-ge4352a0fee49441a32d12e8d8b98c425cfed4a86
Author: liuhongt
Date: Mon Mar
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
Richard Biener changed:
What|Removed |Added
Last reconfirmed||2022-03-28
Ever confirmed|0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #2 from Hongtao.liu ---
> That may be a separate bug, IDK
>
Open PR105072 for it.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #1 from Hongtao.liu ---
pinsrw is under sse2 for both reg and mem operands, but not for pextrw which
requires sse4.1 for memory operands.
10593(define_insn "vec_set_0"
10594 [(set (match_operand:V8_128 0 "register_operand"
10595
