https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85038
--- Comment #2 from Andrew Pinski ---
Note on some aarch64 micro-arch, the zero extend does not take up an issue slot
and is removed in the pipeline before issue. So it might be less than an issue
about the zero extend there except for cache
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85038
--- Comment #1 from Peter Cordes ---
Correction for AArch64: it supports addressing modes with a 64-bit base
register + 32-bit index register with zero or sign extension for the 32-bit
index. But not 32-bit base registers.
As a hack that's