--- Comment #15 from steven at gcc dot gnu dot org 2008-12-15 17:38 ---
Re. comment #14: Yes, I suppose so. Why do you want to remove gcse-las from
mainline. Not that I'm against it -- ideally RTL gcse.c would not work on
memory at all anymore -- but I wouldn't remove gcse-las until we
--- Comment #14 from sergeid at il dot ibm dot com 2008-12-15 07:17 ---
Ok, since this case is the only one where RTL PRE (gcse-las) improves
performance and it can be dealt with at the TreeSSA level, it should be ok to
remove gcse-las from mainline and keep this PR open?
--
http:/
--- Comment #13 from rguenther at suse dot de 2008-12-08 12:40 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
On Mon, 8 Dec 2008, sergeid at il dot ibm dot com wrote:
> --- Comment #12 from sergeid at il dot ibm dot com 2008-12-08 11:53
> ---
> I have to ment
--- Comment #12 from sergeid at il dot ibm dot com 2008-12-08 11:53 ---
I have to mention that tree PRE still don't catch this LOAD with -O3.
Though the patch Richard posted does the job.
(In reply to comment #1)
> It works with -O3 (with partial-partial PRE enabled). At least
> phi-
--- Comment #10 from sergeid at il dot ibm dot com 2008-12-08 10:08 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
Sorry, forgot to attach the patch.(See attached file:
gcse-las-counter.patch)
--- Comment #11 from sergeid at il dot ibm dot com 2008-12-08 10:08 --
--- Comment #9 from sergeid at il dot ibm dot com 2008-12-08 10:03 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
Can you post your gcc configuration options?
I've created and attached a little patch which adds some more information
to dump file. Can you apply it and se
--- Comment #8 from steven at gcc dot gnu dot org 2008-12-04 18:16 ---
Created an attachment (id=16828)
--> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=16828&action=view)
.gcse1 dump of r142405 on ia64-linux
I still don't see why this is caught on powerpc by RTL PRE, but not on ia64
--- Comment #7 from sergeid at il dot ibm dot com 2008-12-04 17:54 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
You're right, it worked for me only on powerpc. This is RTL snippet
_before_ elimination (load + xor + store):
...
(insn 20 19 21 5 ../loop.c:10 (set (reg:
--- Comment #6 from dberlin at gcc dot gnu dot org 2008-12-04 17:35 ---
Subject: Re: TreeSSA-PRE load after store misoptimization
Yes, i'm aware, but again, that is because my recollection is doing
partial antic partial avail with lifetime optimality requires code
placement that we don
--- Comment #5 from steven at gcc dot gnu dot org 2008-12-04 17:27 ---
by_all was there because you made it so on purpose. From tree-ssa-pre.c:
" For the partial anticipation case, we only perform insertion if it
is partially anticipated in some block, and fully available in all
--- Comment #4 from dberlin at gcc dot gnu dot org 2008-12-04 17:14 ---
Subject: Re: TreeSSA-PRE load after store misoptimization
That would be incorrect.
Partial partial (Partial antic, Partial Avail). PRE is necessary to
catch all the cases LCM does (and RTL PRE is LCM based).
LCM in
--- Comment #3 from steven at gcc dot gnu dot org 2008-12-04 17:08 ---
I do not see RTL PRE catch this on ia64, with or without -fgcse-las.
Can you show, please, the RTL dumps before and after GCSE?
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38401
--- Comment #2 from steven at gcc dot gnu dot org 2008-12-04 16:58 ---
If RTL pre can catch this, then so should tree-PRE without enabling
partial-partial PRE.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38401
--- Comment #1 from rguenth at gcc dot gnu dot org 2008-12-04 15:14 ---
It works with -O3 (with partial-partial PRE enabled). At least phi-translation
figures out that *res is zero on the incoming edge.
Un-leashing partial-PRE like with
Index: tree-ssa-pre.c
==
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