[gcc r15-1596] [PATCH 07/11] Handle structs and classes for CodeView

https://gcc.gnu.org/g:4f86d2a5c0246a90d8d20fb325572a97f3ce7080 commit r15-1596-g4f86d2a5c0246a90d8d20fb325572a97f3ce7080 Author: Mark Harmstone Date: Mon Jun 24 23:39:46 2024 -0600 [PATCH 07/11] Handle structs and classes for CodeView Translates DW_TAG_structure_type DIEs into

[gcc r15-1595] [committed][RISC-V] Fix some of the testsuite fallout from late-combine patch

https://gcc.gnu.org/g:41ff74aa581ed38d04c46e6c8839eab48e1b63de commit r15-1595-g41ff74aa581ed38d04c46e6c8839eab48e1b63de Author: Jeff Law Date: Mon Jun 24 23:22:21 2024 -0600 [committed][RISC-V] Fix some of the testsuite fallout from late-combine patch This fixes most, but not

[gcc r15-1594] Replace {FLOAT, {, LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_type

https://gcc.gnu.org/g:55947b32c38a40777aedbd105bd94b43a42c2a10 commit r15-1594-g55947b32c38a40777aedbd105bd94b43a42c2a10 Author: Kewen Lin Date: Tue Jun 25 00:04:53 2024 -0500 Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_type Currently how we

[gcc r15-1593] vms: Replace use of LONG_DOUBLE_TYPE_SIZE

https://gcc.gnu.org/g:7eddf6e857bc79cfa0bee3b9ad89a7e16a81d1e8 commit r15-1593-g7eddf6e857bc79cfa0bee3b9ad89a7e16a81d1e8 Author: Kewen Lin Date: Tue Jun 25 00:04:51 2024 -0500 vms: Replace use of LONG_DOUBLE_TYPE_SIZE Joseph pointed out "floating types should have their mode,

[gcc r15-1592] rust: Replace uses of {FLOAT, {, LONG_}DOUBLE}_TYPE_SIZE

https://gcc.gnu.org/g:bcd1b7a097031d33bc74943bb260d12ff801cf3f commit r15-1592-gbcd1b7a097031d33bc74943bb260d12ff801cf3f Author: Kewen Lin Date: Tue Jun 25 00:04:49 2024 -0500 rust: Replace uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE Joseph pointed out "floating types should have

[gcc r15-1591] go: Replace uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE

https://gcc.gnu.org/g:fafd87830937d5a0eddeb4e1110910ad817c11b4 commit r15-1591-gfafd87830937d5a0eddeb4e1110910ad817c11b4 Author: Kewen Lin Date: Tue Jun 25 00:04:47 2024 -0500 go: Replace uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE Joseph pointed out "floating types should have

[gcc r14-10344] c-family: Add Warning property to Wnrvo option [PR115624]

https://gcc.gnu.org/g:b7157f3930762097210aa24a3f24ed5cafee6672 commit r14-10344-gb7157f3930762097210aa24a3f24ed5cafee6672 Author: Andrew Pinski Date: Mon Jun 24 18:16:13 2024 -0700 c-family: Add Warning property to Wnrvo option [PR115624] This was missing when Wnrvo was added in

[gcc r15-1590] c-family: Add Warning property to Wnrvo option [PR115624]

https://gcc.gnu.org/g:f7747210947a7c66e865c6ac571cce39e2b87caf commit r15-1590-gf7747210947a7c66e865c6ac571cce39e2b87caf Author: Andrew Pinski Date: Mon Jun 24 18:16:13 2024 -0700 c-family: Add Warning property to Wnrvo option [PR115624] This was missing when Wnrvo was added in

[gcc r15-1589] Make transitive relations an oracle option

https://gcc.gnu.org/g:4c8b085820f057d1397d91c1ed1c20bed09eb054 commit r15-1589-g4c8b085820f057d1397d91c1ed1c20bed09eb054 Author: Andrew MacLeod Date: Mon Jun 24 10:29:06 2024 -0400 Make transitive relations an oracle option This patch makes processing of transitive relations

[gcc r15-1587] [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

https://gcc.gnu.org/g:a424318d32103dde827e8507fa27d24d33407ec9 commit r15-1587-ga424318d32103dde827e8507fa27d24d33407ec9 Author: Sergei Lewis Date: Mon Jun 24 14:20:14 2024 -0600 [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension This is primarily Sergei's work, my

[gcc r15-1586] RISC-V: Add dg-remove-option for z* extensions

https://gcc.gnu.org/g:580c37f1ef7db8e7a398184eb8f5d7555124d30a commit r15-1586-g580c37f1ef7db8e7a398184eb8f5d7555124d30a Author: Patrick O'Neill Date: Mon Jun 24 12:06:15 2024 -0700 RISC-V: Add dg-remove-option for z* extensions This introduces testsuite support infra for

[gcc(refs/users/aoliva/heads/testme)] [libstdc++] [testsuite] no libatomic for vxworks

https://gcc.gnu.org/g:441c81173683b53bbc5cba645d860a5f8065fe77 commit 441c81173683b53bbc5cba645d860a5f8065fe77 Author: Alexandre Oliva Date: Mon Jun 24 14:34:27 2024 -0300 [libstdc++] [testsuite] no libatomic for vxworks libatomic hasn't been ported to vxworks. Most of the

[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

https://gcc.gnu.org/g:82ef09057697f0df8557570673a59e501dd49316 commit 82ef09057697f0df8557570673a59e501dd49316 Author: Alexandre Oliva Date: Thu Jun 20 07:26:40 2024 -0300 [testsuite] [arm] [vect] adjust mve-vshr test [PR113281] The test was too optimistic, alas. We used to

[gcc/aoliva/heads/testme] (2 commits) [libstdc++] [testsuite] no libatomic for vxworks

The branch 'aoliva/heads/testme' was updated to point to: 441c8117368... [libstdc++] [testsuite] no libatomic for vxworks It previously pointed to: 7c42cd96b6b... [testsuite] [arm] [vect] adjust mve-vshr test [PR113281] Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE

[gcc r15-1585] Fortran: fix passing of optional dummy as actual to optional argument [PR55978]

https://gcc.gnu.org/g:f02c70dafd384f0c44d7a0920f4a75a30e267045 commit r15-1585-gf02c70dafd384f0c44d7a0920f4a75a30e267045 Author: Harald Anlauf Date: Sun Jun 23 22:36:43 2024 +0200 Fortran: fix passing of optional dummy as actual to optional argument [PR55978]

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()

https://gcc.gnu.org/g:f3fecf54f0a91e8a9b65e1ce6b984324654b2e2d commit f3fecf54f0a91e8a9b65e1ce6b984324654b2e2d Author: Artemiy Volkov Date: Sun Jun 23 14:54:00 2024 -0600 [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move() Presently, the code fragment:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL

https://gcc.gnu.org/g:378cecaed950d1a09ce6b3540f582735ba3e1a89 commit 378cecaed950d1a09ce6b3540f582735ba3e1a89 Author: Jeff Law Date: Sun Jun 23 08:26:25 2024 -0600 [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL Run-of-the-mill checking

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

https://gcc.gnu.org/g:43fd6784e05e28789f53a0ed100cf30d21daa5cc commit 43fd6784e05e28789f53a0ed100cf30d21daa5cc Author: Craig Blackmore Date: Sat Jun 22 22:07:06 2024 -0600 [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests These tests check the sched2 dump, so skip them for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Remove integer vector eqne pattern

https://gcc.gnu.org/g:6d2cbb47ad006038785d56853b1b4c3e83d83b55 commit 6d2cbb47ad006038785d56853b1b4c3e83d83b55 Author: demin.han Date: Sat Jun 22 22:02:02 2024 -0600 [PATCH v2] RISC-V: Remove integer vector eqne pattern We can unify eqne and other comparison operations.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well

https://gcc.gnu.org/g:83ba88a7cba51177fd9f512a78a93f423ab9f0f5 commit 83ba88a7cba51177fd9f512a78a93f423ab9f0f5 Author: Jeff Law Date: Sat Jun 22 10:39:51 2024 -0600 [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well > the test should probably also be skipped on -Oz: >

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Minor cleanup/improvement to bset/binv patterns

https://gcc.gnu.org/g:23e7e8c94fe6a0385d15503d878bfb75c718eb14 commit 23e7e8c94fe6a0385d15503d878bfb75c718eb14 Author: Jeff Law Date: Thu Jun 20 08:43:37 2024 -0600 [RISC-V] Minor cleanup/improvement to bset/binv patterns Changes since V1: Whitespace fixes noted by the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Remove float vector eqne pattern

https://gcc.gnu.org/g:eeead7eee12c4d3bc78c07fe6061c6d922a2dcbc commit eeead7eee12c4d3bc78c07fe6061c6d922a2dcbc Author: demin.han Date: Wed Jun 19 16:21:13 2024 -0600 [PATCH v2] RISC-V: Remove float vector eqne pattern We can unify eqne and other comparison operations.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

https://gcc.gnu.org/g:3eb4898422071a21d72d5ad388b5b5f2af68efe8 commit 3eb4898422071a21d72d5ad388b5b5f2af68efe8 Author: Patrick O'Neill Date: Tue Jun 18 14:40:15 2024 -0700 RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils Binutils 2.42 and before don't support

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9

https://gcc.gnu.org/g:aea32d1c19aaed2b1b80102c6621c33729cd615e commit aea32d1c19aaed2b1b80102c6621c33729cd615e Author: Pan Li Date: Wed Jun 19 21:02:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 9 After the middle-end support the form 9 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10

https://gcc.gnu.org/g:19bab664d3be18130e0889ce86def9e923e5fa23 commit 19bab664d3be18130e0889ce86def9e923e5fa23 Author: Pan Li Date: Wed Jun 19 21:14:31 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 10 After the middle-end support the form 10 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8

https://gcc.gnu.org/g:c353bc5060d1262fbbbce50ca40950aff94eae8b commit c353bc5060d1262fbbbce50ca40950aff94eae8b Author: Pan Li Date: Wed Jun 19 20:38:43 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 8 After the middle-end support the form 8 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7

https://gcc.gnu.org/g:52b0df31d76219a31544e4e13245e4008fdaf2a2 commit 52b0df31d76219a31544e4e13245e4008fdaf2a2 Author: Pan Li Date: Wed Jun 19 20:28:11 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 7 After the middle-end support the form 7 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6

https://gcc.gnu.org/g:8106040edb37de446a9a69d282cce6abf5b9d5d2 commit 8106040edb37de446a9a69d282cce6abf5b9d5d2 Author: Pan Li Date: Wed Jun 19 20:15:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 6 After the middle-end support the form 6 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5

https://gcc.gnu.org/g:7ec128fd9d9a9b49bde6c0b2c1adef53b99f994c commit 7ec128fd9d9a9b49bde6c0b2c1adef53b99f994c Author: Pan Li Date: Wed Jun 19 19:44:52 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 5 After the middle-end support the form 5 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 4

https://gcc.gnu.org/g:f48f96bb2b8550eea44e20cd0c3c6527cac9d113 commit f48f96bb2b8550eea44e20cd0c3c6527cac9d113 Author: Pan Li Date: Wed Jun 19 19:19:23 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 4 After the middle-end support the form 4 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3

https://gcc.gnu.org/g:bee6a1a5ac883bd46255beac7d697720bc31e1f9 commit bee6a1a5ac883bd46255beac7d697720bc31e1f9 Author: Pan Li Date: Wed Jun 19 18:56:51 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 After the middle-end support the form 3 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

https://gcc.gnu.org/g:3d488579847638423bc7884c1752a2fb229a0cce commit 3d488579847638423bc7884c1752a2fb229a0cce Author: Pan Li Date: Mon Jun 17 22:31:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 8 After the middle-end support the form 8 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

https://gcc.gnu.org/g:ae1d941508525968a96ed93fdd3eaa28f77b3497 commit ae1d941508525968a96ed93fdd3eaa28f77b3497 Author: Pan Li Date: Mon Jun 17 22:19:54 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 7 After the middle-end support the form 7 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

https://gcc.gnu.org/g:d3690c6e2ec10ad3970f209ce656e399386a8e3e commit d3690c6e2ec10ad3970f209ce656e399386a8e3e Author: Pan Li Date: Mon Jun 17 22:10:31 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 6 After the middle-end support the form 6 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

https://gcc.gnu.org/g:684d632a2c4c4e230a972ae6f8864e95970aa530 commit 684d632a2c4c4e230a972ae6f8864e95970aa530 Author: Pan Li Date: Mon Jun 17 16:31:26 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 5 After the middle-end support the form 5 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

https://gcc.gnu.org/g:6eae8ad3a3018078fe7e8c662d40a950d022c4fb commit 6eae8ad3a3018078fe7e8c662d40a950d022c4fb Author: Pan Li Date: Mon Jun 17 16:09:13 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 4 After the middle-end support the form 4 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

https://gcc.gnu.org/g:120e57ec19349598b87b51d81c248537a256449c commit 120e57ec19349598b87b51d81c248537a256449c Author: Pan Li Date: Mon Jun 17 14:53:12 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 3 After the middle-end support the form 3 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

https://gcc.gnu.org/g:ae07eb2afcc0c17759ca52ead3067b000787a115 commit ae07eb2afcc0c17759ca52ead3067b000787a115 Author: Pan Li Date: Mon Jun 17 14:39:10 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 After the middle-end support the form 2 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

https://gcc.gnu.org/g:13eae3ea598541647de32a3a81b6188403990565 commit 13eae3ea598541647de32a3a81b6188403990565 Author: Pan Li Date: Tue Jun 18 16:22:59 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12 After the middle-end support the form 12 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

https://gcc.gnu.org/g:0fe89b64995618351f6e0bc05e7c2fad886a3b74 commit 0fe89b64995618351f6e0bc05e7c2fad886a3b74 Author: Pan Li Date: Tue Jun 18 16:14:23 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 After the middle-end support the form 11 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move mode assertion out of conditional branch in emit_insn

https://gcc.gnu.org/g:47b3c4c862f9ce04becda9ab82d28d2f6e54d4f7 commit 47b3c4c862f9ce04becda9ab82d28d2f6e54d4f7 Author: Edwin Lu Date: Fri Jun 14 09:46:01 2024 -0700 RISC-V: Move mode assertion out of conditional branch in emit_insn When emitting insns, we have an early assertion

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vwsll combine on rv32 targets

https://gcc.gnu.org/g:23840c32e5f3bae1f23dc25a10567e50b31b73db commit 23840c32e5f3bae1f23dc25a10567e50b31b73db Author: Edwin Lu Date: Tue Jun 11 13:50:02 2024 -0700 RISC-V: Fix vwsll combine on rv32 targets On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix wrong patch application

https://gcc.gnu.org/g:835bf804a95f0abe3ce09defb98fd11171fedff0 commit 835bf804a95f0abe3ce09defb98fd11171fedff0 Author: Jeff Law Date: Tue Jun 18 12:10:57 2024 -0600 [committed] [RISC-V] Fix wrong patch application Applied the wrong patch which didn't have the final testsuite

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve bset generation when bit position is limited

https://gcc.gnu.org/g:5a8ee7da0905b4c6b9fb9876783a5273d7eda938 commit 5a8ee7da0905b4c6b9fb9876783a5273d7eda938 Author: Jeff Law Date: Tue Jun 18 06:40:40 2024 -0600 [to-be-committed,RISC-V] Improve bset generation when bit position is limited So more work in the ongoing effort

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Handle zero_extract destination for single bit insertions

https://gcc.gnu.org/g:bd78d15abf96a90bb4e2a2f3b2cc6dc638c5ed4b commit bd78d15abf96a90bb4e2a2f3b2cc6dc638c5ed4b Author: Jeff Law Date: Mon Jun 17 17:24:03 2024 -0600 [to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions Combine will use zero_extract

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add configure check for Zaamo/Zalrsc assembler support

https://gcc.gnu.org/g:6af1fde98e28478caa796904fee52be30f14f0e5 commit 6af1fde98e28478caa796904fee52be30f14f0e5 Author: Patrick O'Neill Date: Mon Jun 17 09:46:05 2024 -0700 RISC-V: Add configure check for Zaamo/Zalrsc assembler support Binutils 2.42 and before don't support

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve variable bit set for rv64

https://gcc.gnu.org/g:e0b2a59719a3807695c05681114324dc4b31570f commit e0b2a59719a3807695c05681114324dc4b31570f Author: Jeff Law Date: Mon Jun 17 07:04:13 2024 -0600 [to-be-committed,RISC-V] Improve variable bit set for rv64 Another case of being able to safely use bset for 1 <<

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

https://gcc.gnu.org/g:13a6b20e991ece33f4f016780549bb16a5a00796 commit 13a6b20e991ece33f4f016780549bb16a5a00796 Author: Jeff Law Date: Sun Jun 16 08:36:27 2024 -0600 [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64 Another improvement for generating Zbs instructions.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for vector unsigned SAT_SUB form 2

https://gcc.gnu.org/g:f8ebe0324e14cbc528d8f6f26858969385aa14ae commit f8ebe0324e14cbc528d8f6f26858969385aa14ae Author: Pan Li Date: Sat Jun 15 20:27:01 2024 +0800 RISC-V: Add testcases for vector unsigned SAT_SUB form 2 The previous RISC-V backend .SAT_SUB enabling patch missed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] riscv: Allocate enough space to strcpy() string

https://gcc.gnu.org/g:29b591a941e426e15a9ef4c72f5acfdf58618909 commit 29b591a941e426e15a9ef4c72f5acfdf58618909 Author: Christoph Müllner Date: Fri Jun 14 20:37:04 2024 +0200 riscv: Allocate enough space to strcpy() string I triggered an ICE on Ubuntu 24.04 when compiling code

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the SAT_ARITH test help header files [NFC]

https://gcc.gnu.org/g:252ef61a865a67c63cf40fd93594efee559de339 commit 252ef61a865a67c63cf40fd93594efee559de339 Author: Pan Li Date: Sat Jun 15 10:15:17 2024 +0800 RISC-V: Refine the SAT_ARITH test help header files [NFC] Separate the vector part code to one standalone header

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10

https://gcc.gnu.org/g:ef69f0b9b9af014df3209e787c6e37c301f4f222 commit ef69f0b9b9af014df3209e787c6e37c301f4f222 Author: Pan Li Date: Fri Jun 14 10:08:59 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 After the middle-end support the form 10 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8

https://gcc.gnu.org/g:50afa42a634f3b6de549ef7de413b4bc8ff0bc84 commit 50afa42a634f3b6de549ef7de413b4bc8ff0bc84 Author: Pan Li Date: Fri Jun 14 09:57:22 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 After the middle-end support the form 8 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9

https://gcc.gnu.org/g:6354e412f4b4f969e1360fad98be392177da3fa8 commit 6354e412f4b4f969e1360fad98be392177da3fa8 Author: Pan Li Date: Fri Jun 14 10:03:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 After the middle-end support the form 9 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7

https://gcc.gnu.org/g:daeb32580f74d0dde79a1eb79b4bec9a6f444f74 commit daeb32580f74d0dde79a1eb79b4bec9a6f444f74 Author: Pan Li Date: Fri Jun 14 09:49:22 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 After the middle-end support the form 7 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6

https://gcc.gnu.org/g:6c3406f0f00c2ccf8a5b5e6baf050bfa22579f96 commit 6c3406f0f00c2ccf8a5b5e6baf050bfa22579f96 Author: Pan Li Date: Thu Jun 13 23:05:00 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 After the middle-end support the form 6 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5

https://gcc.gnu.org/g:094e1b811fbd009bca7db60e026ff811ee9551e4 commit 094e1b811fbd009bca7db60e026ff811ee9551e4 Author: Pan Li Date: Thu Jun 13 22:43:31 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 After the middle-end support the form 5 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

https://gcc.gnu.org/g:1aa0928ed9fd4e24dcad9ac5099c70395642883d commit 1aa0928ed9fd4e24dcad9ac5099c70395642883d Author: Pan Li Date: Fri Jun 14 14:54:22 2024 +0800 RISC-V: Bugfix vec_extract v mode iterator restriction mismatch We have vec_extract pattern which takes ZVFHMIN as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4

https://gcc.gnu.org/g:ea6644ded5cd2df55c0cb37a7e21aeecd7a7e3a4 commit ea6644ded5cd2df55c0cb37a7e21aeecd7a7e3a4 Author: Pan Li Date: Thu Jun 13 22:35:21 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 After the middle-end support the form 4 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

https://gcc.gnu.org/g:c63393401c5da881828997484e73bd4f012caaee commit c63393401c5da881828997484e73bd4f012caaee Author: Pan Li Date: Thu Jun 13 22:06:09 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 After the middle-end support the form 3 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for subword atomic loads/stores

https://gcc.gnu.org/g:04989c678e2a2066d486443eb1045247a0ec20a3 commit 04989c678e2a2066d486443eb1045247a0ec20a3 Author: Patrick O'Neill Date: Wed Jun 12 17:10:13 2024 -0700 RISC-V: Add support for subword atomic loads/stores Andrea Parri recently pointed out that we were emitting

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch

https://gcc.gnu.org/g:e80e1db5a63ef41b5477fb80130e556f548db588 commit e80e1db5a63ef41b5477fb80130e556f548db588 Author: Pan Li Date: Thu Jun 13 15:26:59 2024 +0800 RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch We have vec_extract pattern which takes ZVFHMIN as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Test: Move target independent test cases to gcc.dg/torture

https://gcc.gnu.org/g:a457cce60e7031e08e7795ae41819f2929e83fa5 commit a457cce60e7031e08e7795ae41819f2929e83fa5 Author: Pan Li Date: Tue Jun 11 10:56:23 2024 +0800 Test: Move target independent test cases to gcc.dg/torture The test cases of pr115387 are target independent, at

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow any temp register to be used in amo tests

https://gcc.gnu.org/g:92e22468413a16b10ff08c7c3674475f6f8d2976 commit 92e22468413a16b10ff08c7c3674475f6f8d2976 Author: Patrick O'Neill Date: Mon Jun 10 17:00:38 2024 -0700 RISC-V: Allow any temp register to be used in amo tests We artifically restrict the temp registers to be

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix amoadd call arguments

https://gcc.gnu.org/g:759a34e3f26367ce0b2eabd38f8fd03f7bada664 commit 759a34e3f26367ce0b2eabd38f8fd03f7bada664 Author: Patrick O'Neill Date: Mon Jun 10 16:58:12 2024 -0700 RISC-V: Fix amoadd call arguments Update __atomic_add_fetch arguments to be a pointer and value rather

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move amo tests into subfolder

https://gcc.gnu.org/g:9f9724b6a33d39b32d484e4eabe14097a412320c commit 9f9724b6a33d39b32d484e4eabe14097a412320c Author: Patrick O'Neill Date: Mon Jun 10 16:32:11 2024 -0700 RISC-V: Move amo tests into subfolder There's a large number of atomic related testcases in the riscv

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zalrsc amo-op patterns

https://gcc.gnu.org/g:a120ea65ca23b0436f58b99cf30e35c6f1ec9bf3 commit a120ea65ca23b0436f58b99cf30e35c6f1ec9bf3 Author: Patrick O'Neill Date: Wed Feb 7 16:30:30 2024 -0800 RISC-V: Add Zalrsc amo-op patterns All amo patterns can be represented with lrsc sequences. Add these

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zalrsc and Zaamo testsuite support

https://gcc.gnu.org/g:b11365101a0e6afc5bae847d368636ef99a98964 commit b11365101a0e6afc5bae847d368636ef99a98964 Author: Patrick O'Neill Date: Mon Jun 10 14:12:40 2024 -0700 RISC-V: Add Zalrsc and Zaamo testsuite support Convert testsuite infrastructure to use Zalrsc and Zaamo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add basic Zaamo and Zalrsc support

https://gcc.gnu.org/g:73cd4403af9bdfd81c24741a2afac1b53597e148 commit 73cd4403af9bdfd81c24741a2afac1b53597e148 Author: Edwin Lu Date: Wed Feb 7 16:30:28 2024 -0800 RISC-V: Add basic Zaamo and Zalrsc support There is a proposal to split the A extension into two parts: Zaamo and

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned vector int

https://gcc.gnu.org/g:de50942b26eaaf91b472fb6cbb29201476c9dcb3 commit de50942b26eaaf91b472fb6cbb29201476c9dcb3 Author: Pan Li Date: Tue Jun 11 11:04:22 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned vector int As the middle support of .SAT_SUB committed, implement the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Drop dead round_32 test

https://gcc.gnu.org/g:95948af9727cfa8dc6709b4d5719011efc5c47a7 commit 95948af9727cfa8dc6709b4d5719011efc5c47a7 Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test This test is no longer useful. It doesn't test what it was originally

[gcc r15-1584] PR tree-optimization/113673: Avoid load merging when potentially trapping.

https://gcc.gnu.org/g:d8b05aef77443e1d3d8f3f5d2c56ac49a503fee3 commit r15-1584-gd8b05aef77443e1d3d8f3f5d2c56ac49a503fee3 Author: Roger Sayle Date: Mon Jun 24 15:34:03 2024 +0100 PR tree-optimization/113673: Avoid load merging when potentially trapping. This patch fixes PR

[gcc r15-1583] tree-optimization/115602 - SLP CSE results in cycles

https://gcc.gnu.org/g:c43c74f6ec795a586388de7abfdd20a0040f6f16 commit r15-1583-gc43c74f6ec795a586388de7abfdd20a0040f6f16 Author: Richard Biener Date: Mon Jun 24 09:52:39 2024 +0200 tree-optimization/115602 - SLP CSE results in cycles The following prevents SLP CSE to create new

[gcc r15-1582] tree-optimization/115528 - fix vect alignment analysis for outer loop vect

https://gcc.gnu.org/g:2f83ea87ee328d337f87d4430861221be9babe1e commit r15-1582-g2f83ea87ee328d337f87d4430861221be9babe1e Author: Richard Biener Date: Fri Jun 21 13:19:26 2024 +0200 tree-optimization/115528 - fix vect alignment analysis for outer loop vect For outer loop

[gcc r15-1581] Fix MinGW option -mcrtdll=

https://gcc.gnu.org/g:0de0476e47c774db21c94a75d60485a55ec7b5b4 commit r15-1581-g0de0476e47c774db21c94a75d60485a55ec7b5b4 Author: Pali Rohár Date: Sun Jun 23 18:40:59 2024 +0200 Fix MinGW option -mcrtdll= Add missing msvcr40* and msvcrtd* cases to CPP_SPEC and document missing

[gcc r15-1580] Regenerate common.opt.urls

https://gcc.gnu.org/g:a6f7e3ca2961e9315a23ffd99b40f004848f900e commit r15-1580-ga6f7e3ca2961e9315a23ffd99b40f004848f900e Author: Richard Sandiford Date: Mon Jun 24 09:42:16 2024 +0100 Regenerate common.opt.urls gcc/ * common.opt.urls: Regenerate. Diff: ---

[gcc r15-1579] Add a late-combine pass [PR106594]

https://gcc.gnu.org/g:792f97b44ffc5e6a967292b3747fd835e99396e7 commit r15-1579-g792f97b44ffc5e6a967292b3747fd835e99396e7 Author: Richard Sandiford Date: Mon Jun 24 08:43:19 2024 +0100 Add a late-combine pass [PR106594] This patch adds a combine pass that runs late in the

[gcc r15-1578] rtl-ssa: Rework _ignoring interfaces

https://gcc.gnu.org/g:5185274c76cc3b68a38713273779ec29ae4fe5d2 commit r15-1578-g5185274c76cc3b68a38713273779ec29ae4fe5d2 Author: Richard Sandiford Date: Mon Jun 24 08:43:18 2024 +0100 rtl-ssa: Rework _ignoring interfaces rtl-ssa has routines for scanning forwards or backwards for

[gcc r15-1577] tree-optimization/115599 - reassoc qsort comparator issue

https://gcc.gnu.org/g:ae13af26060eb686418ea9c9d455cd665049402d commit r15-1577-gae13af26060eb686418ea9c9d455cd665049402d Author: Richard Biener Date: Sun Jun 23 14:37:53 2024 +0200 tree-optimization/115599 - reassoc qsort comparator issue The compare_repeat_factors comparator