[gcc r15-821] [to-be-committed, v2, RISC-V] Use bclri in constant synthesis

https://gcc.gnu.org/g:401994d60ab38ffa9e63f368f0456eb7b08599be commit r15-821-g401994d60ab38ffa9e63f368f0456eb7b08599be Author: Jeff Law Date: Fri May 24 07:27:00 2024 -0600 [to-be-committed,v2,RISC-V] Use bclri in constant synthesis Testing with Zbs enabled by default showed a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in alloca epilogue expansion

https://gcc.gnu.org/g:106d603005c774ad619103bae3b653c94b80bf9c commit 106d603005c774ad619103bae3b653c94b80bf9c Author: Vineet Gupta Date: Wed Mar 6 15:44:27 2024 -0800 RISC-V: avoid LUI based const mat in alloca epilogue expansion This is continuing on the prev patch in function

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

https://gcc.gnu.org/g:259f9f2c67458b594fec9eac9df0ddb8a5a27867 commit 259f9f2c67458b594fec9eac9df0ddb8a5a27867 Author: Vineet Gupta Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for stack

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Regenerate riscv.opt.urls and i386.opt.urls

https://gcc.gnu.org/g:97fb62e5969841287c275bc12b80fd950a38061b commit 97fb62e5969841287c275bc12b80fd950a38061b Author: Mark Wielaard Date: Mon May 20 13:13:02 2024 +0200 Regenerate riscv.opt.urls and i386.opt.urls risc-v added an -mfence-tso option. i386 removed Xeon Phi ISA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] DSE: Fix ICE after allow vector type in get_stored_val

https://gcc.gnu.org/g:5ef90118a30e49ce73f48a6f3c94129374290b5c commit 5ef90118a30e49ce73f48a6f3c94129374290b5c Author: Pan Li Date: Tue Apr 30 09:42:39 2024 +0800 DSE: Fix ICE after allow vector type in get_stored_val We allowed vector type for get_stored_val when read is less

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:08aaf0da2e4cb4e36df0471e532ddf1acc873e79 commit 08aaf0da2e4cb4e36df0471e532ddf1acc873e79 Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances which

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement -m{, no}fence-tso

https://gcc.gnu.org/g:1b074bdb09654ddd7d0d10ed31133f58df0d656e commit 1b074bdb09654ddd7d0d10ed31133f58df0d656e Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso` instruction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:03f61ba899a4e1025284ee0de2390363694190cc commit 03f61ba899a4e1025284ee0de2390363694190cc Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add

[gcc r15-652] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:e1ce9c37ed68136a99d44c8301990c184ba41849 commit r15-652-ge1ce9c37ed68136a99d44c8301990c184ba41849 Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances

[gcc r15-647] RISC-V: Implement -m{,no}fence-tso

https://gcc.gnu.org/g:a6114c2a691112f9cf5b072c21685d2e43c76d81 commit r15-647-ga6114c2a691112f9cf5b072c21685d2e43c76d81 Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso`

[gcc r13-8777] [committed] Fix RISC-V missing stack tie

https://gcc.gnu.org/g:162c441c9462d073c53dde87258898795bf28a5c commit r13-8777-g162c441c9462d073c53dde87258898795bf28a5c Author: Jeff Law Date: Thu Mar 21 20:41:59 2024 -0600 [committed] Fix RISC-V missing stack tie As some of you know, Raphael has been working on stack-clash

[gcc r15-646] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 commit r15-646-g3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

https://gcc.gnu.org/g:a5445260bd42d74aabe6c11d6207d113aafe2c8c commit a5445260bd42d74aabe6c11d6207d113aafe2c8c Author: Xiao Zeng Date: Wed May 15 16:23:16 2024 +0800 RISC-V: Fix "Nan-box the result of movbf on soft-bf16" 1 According to unpriv-isa spec:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Modify _Bfloat16 to __bf16

https://gcc.gnu.org/g:af9118f721e8d586049ff4a60ff7bc5507478344 commit af9118f721e8d586049ff4a60ff7bc5507478344 Author: Xiao Zeng Date: Fri May 17 13:48:21 2024 +0800 RISC-V: Modify _Bfloat16 to __bf16 According to the description in:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:d6cb9a0d984a6c9ea0b548178a5cf79629be073b commit d6cb9a0d984a6c9ea0b548178a5cf79629be073b Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores more

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:db2b829f4d45c6f14724148d1f8b2066290b3371 commit db2b829f4d45c6f14724148d1f8b2066290b3371 Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv backend as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:17dfc9744f4995d3161eeba104bd86391005769b commit 17dfc9744f4995d3161eeba104bd86391005769b Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch removes

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup some temporally files [NFC]

https://gcc.gnu.org/g:586e678cd18c8d7a72e5f785094d911a098092ff commit 586e678cd18c8d7a72e5f785094d911a098092ff Author: Pan Li Date: Fri May 17 07:45:19 2024 +0800 RISC-V: Cleanup some temporally files [NFC] Just notice some temporally files under gcc/config/riscv, deleted as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorizable early exit testsuite

https://gcc.gnu.org/g:c1ad575242ff3dee66f2775412b1c65efbc2269b commit c1ad575242ff3dee66f2775412b1c65efbc2269b Author: Pan Li Date: Thu May 16 10:04:10 2024 +0800 RISC-V: Enable vectorizable early exit testsuite After we supported vectorizable early exit in RISC-V, we would like

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vectorizable early exit with vcond_mask_len

https://gcc.gnu.org/g:b1aab03aed7f3d8c9b104b5f596e7e9853b8d5e6 commit b1aab03aed7f3d8c9b104b5f596e7e9853b8d5e6 Author: Pan Li Date: Thu May 16 10:02:40 2024 +0800 RISC-V: Implement vectorizable early exit with vcond_mask_len After we support the loop lens for the vectorizable,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support loop len in vectorizable early exit

https://gcc.gnu.org/g:4ec3a6b6022c1853cfd5866dea0324a4002413b2 commit 4ec3a6b6022c1853cfd5866dea0324a4002413b2 Author: Pan Li Date: Thu May 16 09:58:13 2024 +0800 Vect: Support loop len in vectorizable early exit This patch adds early break auto-vectorization support for target

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int

https://gcc.gnu.org/g:51b69c80a76ba767ed166e93a569a84dae445b23 commit 51b69c80a76ba767ed166e93a569a84dae445b23 Author: Pan Li Date: Wed May 15 10:14:05 2024 +0800 Internal-fn: Support new IFN SAT_ADD for unsigned scalar int This patch would like to add the middle-end presentation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support new IFN SAT_ADD for unsigned vector int

https://gcc.gnu.org/g:674362d73e964815cdb700edd9fedbfc34c24c21 commit 674362d73e964815cdb700edd9fedbfc34c24c21 Author: Pan Li Date: Wed May 15 10:14:06 2024 +0800 Vect: Support new IFN SAT_ADD for unsigned vector int For vectorize, we leverage the existing vect pattern recog to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests

https://gcc.gnu.org/g:faf2f9ed73969d838026027566473bde14db748b commit faf2f9ed73969d838026027566473bde14db748b Author: Christoph Müllner Date: Thu May 16 09:53:47 2024 +0200 RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests The tests cmpmemsi-1.c and cpymemsi-1.c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zvfbfwma extension to the -march= option

https://gcc.gnu.org/g:67195fbc4deac8659d8f65ab922416ac451ae5bb commit 67195fbc4deac8659d8f65ab922416ac451ae5bb Author: Xiao Zeng Date: Wed May 15 10:03:40 2024 +0800 RISC-V: Add Zvfbfwma extension to the -march= option This patch would like to add new sub extension (aka Zvfbfwma)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Add missing hunk in recent change.

https://gcc.gnu.org/g:45c5684c8242add5e97a392374dc160a6e68f2f0 commit 45c5684c8242add5e97a392374dc160a6e68f2f0 Author: Jeff Law Date: Wed May 15 17:05:24 2024 -0600 Add missing hunk in recent change. gcc/ * config/riscv/riscv-string.cc: Add missing hunk from last

[gcc r15-527] Add missing hunk in recent change.

https://gcc.gnu.org/g:d7e6fe0f72ad41b8361f927d2796dbc275347297 commit r15-527-gd7e6fe0f72ad41b8361f927d2796dbc275347297 Author: Jeff Law Date: Wed May 15 17:05:24 2024 -0600 Add missing hunk in recent change. gcc/ * config/riscv/riscv-string.cc: Add missing hunk from

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [v2, 2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation

https://gcc.gnu.org/g:72e6ff2bcf293116099988ebd367182cba699e9b commit 72e6ff2bcf293116099988ebd367182cba699e9b Author: Christoph Müllner Date: Wed May 15 12:19:40 2024 -0600 [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation We have an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [v2, 1/2] RISC-V: Add cmpmemsi expansion

https://gcc.gnu.org/g:d57dfea6e051695349fb9f6da1c30899b7f5 commit d57dfea6e051695349fb9f6da1c30899b7f5 Author: Christoph Müllner Date: Wed May 15 12:18:20 2024 -0600 [v2,1/2] RISC-V: Add cmpmemsi expansion GCC has a generic cmpmemsi expansion via the by-pieces framework,

[gcc r15-525] [v2, 2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation

https://gcc.gnu.org/g:1fbbae1d4ba3618a3da829a6d7e11a1606a583b3 commit r15-525-g1fbbae1d4ba3618a3da829a6d7e11a1606a583b3 Author: Christoph Müllner Date: Wed May 15 12:19:40 2024 -0600 [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation We have an

[gcc r15-524] [v2,1/2] RISC-V: Add cmpmemsi expansion

https://gcc.gnu.org/g:4bf1aa1ab90dd487fadc27c86523ec3562b2d2fe commit r15-524-g4bf1aa1ab90dd487fadc27c86523ec3562b2d2fe Author: Christoph Müllner Date: Wed May 15 12:18:20 2024 -0600 [v2,1/2] RISC-V: Add cmpmemsi expansion GCC has a generic cmpmemsi expansion via the by-pieces

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Test cbo.zero expansion for rv32

https://gcc.gnu.org/g:f3d5808070acf09d4ca1da5f5e692be52e3a73a6 commit f3d5808070acf09d4ca1da5f5e692be52e3a73a6 Author: Christoph Müllner Date: Wed May 15 01:34:54 2024 +0200 RISC-V: Test cbo.zero expansion for rv32 We had an issue when expanding via cmo-zero for RV32. This

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight

https://gcc.gnu.org/g:59e6343f99eb53da07bbd6198f083ce1bbdf20d8 commit 59e6343f99eb53da07bbd6198f083ce1bbdf20d8 Author: Christoph Müllner Date: Mon Apr 29 02:53:20 2024 +0200 RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight The current implementation of

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: add tests for overlapping mem ops

https://gcc.gnu.org/g:ad0413b832400aa9e81e20070b3ef6b0a9a6d888 commit ad0413b832400aa9e81e20070b3ef6b0a9a6d888 Author: Christoph Müllner Date: Mon Apr 29 03:06:52 2024 +0200 RISC-V: add tests for overlapping mem ops A recent patch added the field overlap_op_by_pieces to the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test cases for cpymem expansion

https://gcc.gnu.org/g:0dcd2d26d0da77af7f173b6c0d79a7f5ea25c642 commit 0dcd2d26d0da77af7f173b6c0d79a7f5ea25c642 Author: Christoph Müllner Date: Wed May 1 16:54:42 2024 +0200 RISC-V: Add test cases for cpymem expansion We have two mechanisms in the RISC-V backend that expand

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow unaligned accesses in cpymemsi expansion

https://gcc.gnu.org/g:69408db9b2b3ede055f4392f9d30be33804eec77 commit 69408db9b2b3ede055f4392f9d30be33804eec77 Author: Christoph Müllner Date: Wed May 1 18:50:38 2024 +0200 RISC-V: Allow unaligned accesses in cpymemsi expansion The RISC-V cpymemsi expansion is called, whenever

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Fix rv32 issues with recent zicboz work

https://gcc.gnu.org/g:75a06302ef660397001d67afc1fb4d22e6da5870 commit 75a06302ef660397001d67afc1fb4d22e6da5870 Author: Jeff Law Date: Tue May 14 22:50:15 2024 -0600 [committed] Fix rv32 issues with recent zicboz work I should have double-checked the CI system before pushing

[gcc r15-500] [committed] Fix rv32 issues with recent zicboz work

https://gcc.gnu.org/g:e410ad74e5e4589aeb666aa298b2f933e7b5d9e7 commit r15-500-ge410ad74e5e4589aeb666aa298b2f933e7b5d9e7 Author: Jeff Law Date: Tue May 14 22:50:15 2024 -0600 [committed] Fix rv32 issues with recent zicboz work I should have double-checked the CI system before

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Remove redundant AND in shift-add sequence

https://gcc.gnu.org/g:9de32107d731fbbf15096d065bf706bb9aff94f6 commit 9de32107d731fbbf15096d065bf706bb9aff94f6 Author: Jeff Law Date: Tue May 14 18:17:59 2024 -0600 [to-be-committed,RISC-V] Remove redundant AND in shift-add sequence So this patch allows us to eliminate an

[gcc r15-497] [to-be-committed, RISC-V] Remove redundant AND in shift-add sequence

https://gcc.gnu.org/g:32ff344d57d56fddb66c4976b5651345d40b7157 commit r15-497-g32ff344d57d56fddb66c4976b5651345d40b7157 Author: Jeff Law Date: Tue May 14 18:17:59 2024 -0600 [to-be-committed,RISC-V] Remove redundant AND in shift-add sequence So this patch allows us to eliminate

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const materialization ... [part of PR/106265]

https://gcc.gnu.org/g:de257cc78146b0e518b272de5afc3faa9bbf3669 commit de257cc78146b0e518b272de5afc3faa9bbf3669 Author: Vineet Gupta Date: Mon May 13 11:45:55 2024 -0700 RISC-V: avoid LUI based const materialization ... [part of PR/106265] ... if the constant can be represented as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero

https://gcc.gnu.org/g:f9a0426cdbd0d1e796cd0a9bcd39d31e3d2df018 commit f9a0426cdbd0d1e796cd0a9bcd39d31e3d2df018 Author: Christoph Müllner Date: Tue May 14 09:21:17 2024 -0600 [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero The Zicboz extension offers the cbo.zero

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe

https://gcc.gnu.org/g:0db572dff53572f4c471ec588c7328a33f2cb6ab commit 0db572dff53572f4c471ec588c7328a33f2cb6ab Author: Christoph Müllner Date: Tue May 14 09:20:18 2024 -0600 [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe Let's add '\t' to the instruction match pattern to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [1/3] expr: Export clear_by_pieces()

https://gcc.gnu.org/g:5b00e29d1833dee69e1146f13a8d8a37dadfa31a commit 5b00e29d1833dee69e1146f13a8d8a37dadfa31a Author: Christoph Müllner Date: Tue May 14 09:19:13 2024 -0600 [1/3] expr: Export clear_by_pieces() Make clear_by_pieces() available to other parts of the compiler,

[gcc r15-489] [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe

https://gcc.gnu.org/g:21855f960141c1811d6a5f6ad3b2065f20d4b353 commit r15-489-g21855f960141c1811d6a5f6ad3b2065f20d4b353 Author: Christoph Müllner Date: Tue May 14 09:20:18 2024 -0600 [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe Let's add '\t' to the instruction match

[gcc r15-490] [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero

https://gcc.gnu.org/g:54ba8d44bbd703bca6984700b4d6f978890097e2 commit r15-490-g54ba8d44bbd703bca6984700b4d6f978890097e2 Author: Christoph Müllner Date: Tue May 14 09:21:17 2024 -0600 [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero The Zicboz extension offers the

[gcc r15-488] [1/3] expr: Export clear_by_pieces()

https://gcc.gnu.org/g:e6e41b68fd805ab126895a20bb9670442b198f62 commit r15-488-ge6e41b68fd805ab126895a20bb9670442b198f62 Author: Christoph Müllner Date: Tue May 14 09:19:13 2024 -0600 [1/3] expr: Export clear_by_pieces() Make clear_by_pieces() available to other parts of the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage

https://gcc.gnu.org/g:a39fd3b589c57f3d2860f73d255902bbdef1a51c commit a39fd3b589c57f3d2860f73d255902bbdef1a51c Author: Jeff Law Date: Sun May 12 07:05:43 2024 -0600 [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage Overnight testing showed a small number

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix format issue for trailing operator [NFC]

https://gcc.gnu.org/g:0c1a07d6e5b30aad71798aa7c37fc80bd19b7f63 commit 0c1a07d6e5b30aad71798aa7c37fc80bd19b7f63 Author: Pan Li Date: Tue May 14 09:38:55 2024 +0800 RISC-V: Fix format issue for trailing operator [NFC] This patch would like to fix below format issue of trailing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve AND with some constants

https://gcc.gnu.org/g:c6ed1bc38b17d650ae678b7cac28ce8c2692eb09 commit c6ed1bc38b17d650ae678b7cac28ce8c2692eb09 Author: Jeff Law Date: Mon May 13 17:37:46 2024 -0600 [to-be-committed,RISC-V] Improve AND with some constants If we have an AND with a constant operand and the constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

https://gcc.gnu.org/g:7d135c53cf480c99b6fa883569e9b8d55ed92ea5 commit 7d135c53cf480c99b6fa883569e9b8d55ed92ea5 Author: Pan Li Date: Sat May 11 15:25:28 2024 +0800 RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar For the vfw vx format RVV intrinsic, the scalar type

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve single inverted bit extraction - v3

https://gcc.gnu.org/g:8be088a0f395047189e139d4c791cfc2275898b9 commit 8be088a0f395047189e139d4c791cfc2275898b9 Author: Jeff Law Date: Mon May 13 07:14:08 2024 -0600 [to-be-committed,RISC-V] Improve single inverted bit extraction - v3 So this patch fixes a minor code generation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve usage of slli.uw in constant synthesis

https://gcc.gnu.org/g:71edaf678fae607d7c8ce28ace9a321af711799b commit 71edaf678fae607d7c8ce28ace9a321af711799b Author: Jeff Law Date: Sun May 12 07:12:04 2024 -0600 [to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesis And an improvement to using slli.uw...

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Use shNadd for constant synthesis

https://gcc.gnu.org/g:28db6a196e3251908df676d7c5e9626d29d37e5e commit 28db6a196e3251908df676d7c5e9626d29d37e5e Author: Jeff Law Date: Fri May 10 13:49:44 2024 -0600 [RISC-V] Use shNadd for constant synthesis So here's the next idiom to improve constant synthesis. The

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code or comment [NFC]

https://gcc.gnu.org/g:11c50b62894f2f9487063b1b2906bb0c8981fa5d commit 11c50b62894f2f9487063b1b2906bb0c8981fa5d Author: Kito Cheng Date: Tue May 7 10:18:58 2024 +0800 RISC-V: Fix typos in code or comment [NFC] Just found some typo when fixing bugs and then use aspell to find few

[gcc r15-443] Revert "[PATCH v2 1/3] RISC-V: movmem for RISCV with V extension"

https://gcc.gnu.org/g:04ee1f788ceaa4c7f777ff3b9441ae076191439c commit r15-443-g04ee1f788ceaa4c7f777ff3b9441ae076191439c Author: Jeff Law Date: Mon May 13 21:42:38 2024 -0600 Revert "[PATCH v2 1/3] RISC-V: movmem for RISCV with V extension" This reverts commit

[gcc r15-440] [to-be-committed, RISC-V] Improve AND with some constants

https://gcc.gnu.org/g:158aa1b65ce29d5e58182782de66292c51774d71 commit r15-440-g158aa1b65ce29d5e58182782de66292c51774d71 Author: Jeff Law Date: Mon May 13 17:37:46 2024 -0600 [to-be-committed,RISC-V] Improve AND with some constants If we have an AND with a constant operand and the

[gcc r15-439] [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension

https://gcc.gnu.org/g:df15eb15b5f820321c81efc75f0af13ff8c0dd5b commit r15-439-gdf15eb15b5f820321c81efc75f0af13ff8c0dd5b Author: Sergei Lewis Date: Mon May 13 17:32:24 2024 -0600 [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension This patchset permits generation of inlined

[gcc r15-432] [to-be-committed, RISC-V] Improve single inverted bit extraction - v3

https://gcc.gnu.org/g:0c585c8d0dd85601a8d116ada99126a48c8ce9fd commit r15-432-g0c585c8d0dd85601a8d116ada99126a48c8ce9fd Author: Jeff Law Date: Mon May 13 07:14:08 2024 -0600 [to-be-committed,RISC-V] Improve single inverted bit extraction - v3 So this patch fixes a minor code

[gcc r15-389] [to-be-committed, RISC-V] Improve usage of slli.uw in constant synthesis

https://gcc.gnu.org/g:83fb5e6f382ea99ca0e2a0afeb25a9f78909f25f commit r15-389-g83fb5e6f382ea99ca0e2a0afeb25a9f78909f25f Author: Jeff Law Date: Sun May 12 07:12:04 2024 -0600 [to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesis And an improvement to using

[gcc r15-388] [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage

https://gcc.gnu.org/g:77a28ed91b2a527b9006ee1a220b468756b43eca commit r15-388-g77a28ed91b2a527b9006ee1a220b468756b43eca Author: Jeff Law Date: Sun May 12 07:05:43 2024 -0600 [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage Overnight testing showed a

[gcc r15-384] [PATCH v4 4/4] Output S_COMPILE3 symbol in CodeView debug section

https://gcc.gnu.org/g:1da83fece2963cfe0df57ac5e85dd1f92427ca70 commit r15-384-g1da83fece2963cfe0df57ac5e85dd1f92427ca70 Author: Mark Harmstone Date: Sat May 11 08:24:59 2024 -0600 [PATCH v4 4/4] Output S_COMPILE3 symbol in CodeView debug section Outputs the S_COMPILE3 symbol in

[gcc r15-383] [PATCH v2 3/4] Output line numbers in CodeView section

https://gcc.gnu.org/g:1f129e5e2b74c20a757f2809792af229b551b09b commit r15-383-g1f129e5e2b74c20a757f2809792af229b551b09b Author: Mark Harmstone Date: Sat May 11 08:19:53 2024 -0600 [PATCH v2 3/4] Output line numbers in CodeView section Outputs the DEBUG_S_LINES block in the

[gcc r15-382] [PATCH v2 2/4] Output file checksums in CodeView section

https://gcc.gnu.org/g:ed6690a0ca911138abd4d707510fd03ef188a28b commit r15-382-ged6690a0ca911138abd4d707510fd03ef188a28b Author: Mark Harmstone Date: Sat May 11 08:15:43 2024 -0600 [PATCH v2 2/4] Output file checksums in CodeView section Outputs the file name and MD5 hash of the

[gcc r15-381] [PATCH v2 1/4] Support for CodeView debugging format

https://gcc.gnu.org/g:36781ef8fd26eb9a0686957e7bac8f5ccc5ecc3f commit r15-381-g36781ef8fd26eb9a0686957e7bac8f5ccc5ecc3f Author: Mark Harmstone Date: Sat May 11 08:08:50 2024 -0600 [PATCH v2 1/4] Support for CodeView debugging format This patch and the following add initial

[gcc r15-367] [RISC-V] Use shNadd for constant synthesis

https://gcc.gnu.org/g:dbbd059b49edc936769737204f5c270d8d6ff553 commit r15-367-gdbbd059b49edc936769737204f5c270d8d6ff553 Author: Jeff Law Date: Fri May 10 13:49:44 2024 -0600 [RISC-V] Use shNadd for constant synthesis So here's the next idiom to improve constant synthesis.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

https://gcc.gnu.org/g:13d1b47251a94a67d698d4283caf754382ee27ea commit 13d1b47251a94a67d698d4283caf754382ee27ea Author: Jeff Law Date: Thu May 9 21:07:06 2024 -0600 [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation This fixes a minor

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make full-vec-move1.c test robust for optimization

https://gcc.gnu.org/g:788ed48d01b4fb85689ae1d7a0033cb05a48637f commit 788ed48d01b4fb85689ae1d7a0033cb05a48637f Author: Pan Li Date: Thu May 9 10:56:46 2024 +0800 RISC-V: Make full-vec-move1.c test robust for optimization During investigate the support of early break autovec, we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add tests for cpymemsi expansion

https://gcc.gnu.org/g:2bb25f97841524649fef9d58ce84ca71748e2f2b commit 2bb25f97841524649fef9d58ce84ca71748e2f2b Author: Christoph Müllner Date: Thu Apr 11 12:07:10 2024 +0200 RISC-V: Add tests for cpymemsi expansion cpymemsi expansion was available for RISC-V since the initial

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

https://gcc.gnu.org/g:b59bc760740eccd8f7b76d218ed759d9ae6604c8 commit b59bc760740eccd8f7b76d218ed759d9ae6604c8 Author: Xiao Zeng Date: Wed May 8 14:00:58 2024 -0600 [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16 1 This patch implements the Nan-box of bf16.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

https://gcc.gnu.org/g:f273ad20d6b2b3f196a0c99a5a0c419cc13d862a commit f273ad20d6b2b3f196a0c99a5a0c419cc13d862a Author: Jeff Law Date: Wed May 8 13:44:00 2024 -0600 [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis Reposting without the patch that

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshr3_zero_extend_4

https://gcc.gnu.org/g:b6dc4a54639ee85a425f46b86e152d99d209ffa4 commit b6dc4a54639ee85a425f46b86e152d99d209ffa4 Author: Christoph Müllner Date: Tue May 7 22:23:26 2024 +0200 RISC-V: Cover sign-extensions in lshr3_zero_extend_4 The lshr3_zero_extend_4 pattern targets bit extraction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add zero_extract support for rv64gc

https://gcc.gnu.org/g:38fc117452afa21fac0ca3f743fc09d35c3f8c5c commit 38fc117452afa21fac0ca3f743fc09d35c3f8c5c Author: Christoph Müllner Date: Mon May 6 12:33:32 2024 +0200 RISC-V: Add zero_extract support for rv64gc The combiner attempts to optimize a zero-extension of a logical

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

https://gcc.gnu.org/g:9041a047fe957232d9f9127791a08643b1087a36 commit 9041a047fe957232d9f9127791a08643b1087a36 Author: Christoph Müllner Date: Tue May 7 23:26:02 2024 +0200 RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 The pattern lshrsi3_zero_extend_2 extracts the MSB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test for sraiw-31 special case

https://gcc.gnu.org/g:9a81321828844a7b663c78a9415770a247980e71 commit 9a81321828844a7b663c78a9415770a247980e71 Author: Christoph Müllner Date: Tue May 7 22:59:44 2024 +0200 RISC-V: Add test for sraiw-31 special case We already optimize a sign-extension of a right-shift by 31 in

[gcc r15-354] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

https://gcc.gnu.org/g:bfb88b1406cdd8d3f97e280b0d63529aa925f18a commit r15-354-gbfb88b1406cdd8d3f97e280b0d63529aa925f18a Author: Jeff Law Date: Thu May 9 21:07:06 2024 -0600 [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation This fixes a

[gcc r15-333] [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

https://gcc.gnu.org/g:ce51e6727c9d69bbab0e766c449e60fd41f5f2f9 commit r15-333-gce51e6727c9d69bbab0e766c449e60fd41f5f2f9 Author: Xiao Zeng Date: Wed May 8 14:00:58 2024 -0600 [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16 1 This patch implements the Nan-box of

[gcc r15-332] [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

https://gcc.gnu.org/g:1c234097487927a4388ddcc690b63597bb3a90dc commit r15-332-g1c234097487927a4388ddcc690b63597bb3a90dc Author: Jeff Law Date: Wed May 8 13:44:00 2024 -0600 [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis Reposting without the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning

https://gcc.gnu.org/g:39c05d26b53dcfaede63414a21cc9f769bae98f1 commit 39c05d26b53dcfaede63414a21cc9f769bae98f1 Author: Jeff Law Date: Tue May 7 15:34:16 2024 -0600 [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning Per quick email exchange with Palmer. Given

[gcc r15-306] [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning

https://gcc.gnu.org/g:9f14f1978260148d4d6208dfd73df1858e623758 commit r15-306-g9f14f1978260148d4d6208dfd73df1858e623758 Author: Jeff Law Date: Tue May 7 15:34:16 2024 -0600 [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning Per quick email exchange with

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P

https://gcc.gnu.org/g:07f793b32359e37191b2bda2a4e8cac8428648e8 commit 07f793b32359e37191b2bda2a4e8cac8428648e8 Author: Christoph Müllner Date: Tue May 7 15:16:21 2024 -0600 [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P This is almost exclusively work from

[gcc r15-305] [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P

https://gcc.gnu.org/g:300393484dbfa9fd3891174ea47aa3fb41915abc commit r15-305-g300393484dbfa9fd3891174ea47aa3fb41915abc Author: Christoph Müllner Date: Tue May 7 15:16:21 2024 -0600 [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P This is almost exclusively

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] [PATCH v2] Enable inlining str* by default

https://gcc.gnu.org/g:8b5321bc863bfc9920676c33295644cbebfd0a05 commit 8b5321bc863bfc9920676c33295644cbebfd0a05 Author: Jeff Law Date: Tue May 7 11:43:09 2024 -0600 [RISC-V] [PATCH v2] Enable inlining str* by default So with Chrstoph's patches from late 2022 we've had the ability

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

https://gcc.gnu.org/g:c396fa61e71313cdfcb384bd0fb74f7d3b972d30 commit c396fa61e71313cdfcb384bd0fb74f7d3b972d30 Author: Xiao Zeng Date: Mon May 6 15:57:37 2024 -0600 [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option This patch would like to add new sub extension (aka

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcase for PR114749.

https://gcc.gnu.org/g:cd0e329128a349ff58b75de14e1c877cce9abffc commit cd0e329128a349ff58b75de14e1c877cce9abffc Author: Robin Dapp Date: Mon May 6 15:51:37 2024 -0600 RISC-V: Add testcase for PR114749. this adds a test case for PR114749. Going to commit as obvious unless

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Add support for _Bfloat16

https://gcc.gnu.org/g:af9ec7bb55674b09434ff821ee496558ca8dc4c3 commit af9ec7bb55674b09434ff821ee496558ca8dc4c3 Author: Xiao Zeng Date: Mon May 6 15:39:12 2024 -0600 [RISC-V] Add support for _Bfloat16 1 At point , BF16 has already

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Document -mcmodel=large

https://gcc.gnu.org/g:6b0b0128c4f3fed4dff92c489017b7504c7f970b commit 6b0b0128c4f3fed4dff92c489017b7504c7f970b Author: Palmer Dabbelt Date: Mon May 6 15:34:26 2024 -0600 RISC-V: Document -mcmodel=large This slipped through the cracks. Probably also NEWS-worthy.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] So another constant synthesis improvement.

https://gcc.gnu.org/g:3ccf8a5463d9a606515e141a7f582683115d985b commit 3ccf8a5463d9a606515e141a7f582683115d985b Author: Jeff Law Date: Mon May 6 15:27:43 2024 -0600 So another constant synthesis improvement. In this patch we're looking at cases where we'd like to be able to use

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: miscll comment fixes [NFC]

https://gcc.gnu.org/g:3d0f38b394e6c5f4bb93ce2047dd985ea7e081af commit 3d0f38b394e6c5f4bb93ce2047dd985ea7e081af Author: Vineet Gupta Date: Tue Mar 1 03:45:19 2022 -0800 RISC-V: miscll comment fixes [NFC] gcc/ChangeLog: * config/riscv/riscv.cc: Comment updates.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

https://gcc.gnu.org/g:9ba5c71aeab72bf5a773eaeaaf96a03520c3da9f commit 9ba5c71aeab72bf5a773eaeaaf96a03520c3da9f Author: Jeff Law Date: Thu May 2 17:13:12 2024 -0600 [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits The CI system tripped an execution failure for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

https://gcc.gnu.org/g:0099c20adb23b71718d4c6f3937fd126f1a931e4 commit 0099c20adb23b71718d4c6f3937fd126f1a931e4 Author: Jeff Law Date: Thu May 2 14:06:22 2024 -0600 [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set In doing some preparation work for using

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Trivial pattern cleanup

https://gcc.gnu.org/g:1985c80b0470848d6362e8f769744ed6b7ed743d commit 1985c80b0470848d6362e8f769744ed6b7ed743d Author: Jeff Law Date: Wed May 1 12:43:37 2024 -0600 [committed] [RISC-V] Trivial pattern cleanup As I was reviewing and cleaning up some internal work, I noticed a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

https://gcc.gnu.org/g:63c91bfa7fae1716b23b67cc4e614e379b06f8f6 commit 63c91bfa7fae1716b23b67cc4e614e379b06f8f6 Author: Jeff Law Date: Thu May 2 08:42:32 2024 -0600 [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets The new round_32.c and round_64.c tests

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix detection of store pair fusion cases

https://gcc.gnu.org/g:305a5d2d9a9394579d132364c0fd1ca9e95c9f4c commit 305a5d2d9a9394579d132364c0fd1ca9e95c9f4c Author: Jeff Law Date: Wed May 1 11:28:41 2024 -0600 [committed] [RISC-V] Fix detection of store pair fusion cases We've got the ability to count the number of store

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] This is almost exclusively Jivan's work. His original post:

https://gcc.gnu.org/g:7fd192a0af22aa524685692c086ea1ffe5b0d789 commit 7fd192a0af22aa524685692c086ea1ffe5b0d789 Author: Jivan Hakobyan Date: Tue Apr 30 09:44:02 2024 -0600 This is almost exclusively Jivan's work. His original post: >

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the condition for add additional vars in RVV cost model

https://gcc.gnu.org/g:48b653eb14f8bde7772cf1f2d674bdd9c75302bd commit 48b653eb14f8bde7772cf1f2d674bdd9c75302bd Author: demin.han Date: Tue Mar 26 16:52:12 2024 +0800 RISC-V: Refine the condition for add additional vars in RVV cost model The adjacent_dr_p is sufficient and

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix parsing of Zic* extensions

https://gcc.gnu.org/g:cd78056ad4b3b8a27b3e17dd29dc81d3e28c7719 commit cd78056ad4b3b8a27b3e17dd29dc81d3e28c7719 Author: Christoph Müllner Date: Mon Apr 29 00:46:06 2024 +0200 RISC-V: Fix parsing of Zic* extensions The extension parsing table entries for a range of Zic* extensions

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add -X to link spec

https://gcc.gnu.org/g:96a6647f966a7ec24d07f2960956c71c1ca320c3 commit 96a6647f966a7ec24d07f2960956c71c1ca320c3 Author: Fangrui Song Date: Fri Apr 26 18:14:33 2024 -0700 RISC-V: Add -X to link spec --discard-locals (-X) instructs the linker to remove local .L* symbols, which

[gcc/riscv/heads/gcc-14-with-riscv-opts] (40 commits) [RISC-V] [PATCH v2] Enable inlining str* by default

The branch 'riscv/heads/gcc-14-with-riscv-opts' was updated to point to: 8b5321bc863b... [RISC-V] [PATCH v2] Enable inlining str* by default It previously pointed to: af8ad1d874dc... [committed][RISC-V] Fix nearbyint failure on rv32 and forma Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO

[gcc r15-299] [RISC-V] [PATCH v2] Enable inlining str* by default

https://gcc.gnu.org/g:1139f38e798181572121657e5b267a9698edb62f commit r15-299-g1139f38e798181572121657e5b267a9698edb62f Author: Jeff Law Date: Tue May 7 11:43:09 2024 -0600 [RISC-V] [PATCH v2] Enable inlining str* by default So with Chrstoph's patches from late 2022 we've had the

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