[gcc r16-3476] RISC-V: Add test case for unsigned scalar SAT_MUL form 4

https://gcc.gnu.org/g:af979624128b24303c2e29b3f2535445877056ec commit r16-3476-gaf979624128b24303c2e29b3f2535445877056ec Author: Pan Li Date: Sun Aug 24 16:36:00 2025 +0800 RISC-V: Add test case for unsigned scalar SAT_MUL form 4 The form 4 of unsigned scalar SAT_MUL is covered in

[gcc r16-3450] RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:52d5fc64a4fa71d78078110bb9fa3d972a743a2a commit r16-3450-g52d5fc64a4fa71d78078110bb9fa3d972a743a2a Author: Pan Li Date: Thu Aug 28 10:36:35 2025 +0800 RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0, 1 and 15 Add asm dump chec

[gcc r16-3451] RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:0a44e22df9a0ae0165fed1a5ae39dccc5621a86e commit r16-3451-g0a44e22df9a0ae0165fed1a5ae39dccc5621a86e Author: Pan Li Date: Thu Aug 28 10:39:24 2025 +0800 RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned combine with GR2VR cost 0, 1 and 15 Add asm dump ch

[gcc r16-3449] RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on GR2VR cost

https://gcc.gnu.org/g:44054e62064510d7647344e79208fb14408600dc commit r16-3449-g44054e62064510d7647344e79208fb14408600dc Author: Pan Li Date: Thu Aug 28 10:33:54 2025 +0800 RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on GR2VR cost This patch would like to combine the ve

[gcc r16-3384] RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:74f139fa21da39b03f6dae8597959088e81b6130 commit r16-3384-g74f139fa21da39b03f6dae8597959088e81b6130 Author: Pan Li Date: Tue Aug 19 09:32:22 2025 +0800 RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15 Add asm dump che

[gcc r16-3383] RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:ed2f4bff8bbe7645396c39c924c7e6f1e2af56d6 commit r16-3383-ged2f4bff8bbe7645396c39c924c7e6f1e2af56d6 Author: Pan Li Date: Tue Aug 19 09:30:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15 Add asm dump check

[gcc r16-3382] RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost

https://gcc.gnu.org/g:25037a02716ad0da0f4987960b815dec1f014b1e commit r16-3382-g25037a02716ad0da0f4987960b815dec1f014b1e Author: Pan Li Date: Sat Aug 23 12:55:50 2025 +0800 RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-3346] Match: Add form 3 for unsigned SAT_MUL

https://gcc.gnu.org/g:f2794c206f112547907ed010b541146dc005d37e commit r16-3346-gf2794c206f112547907ed010b541146dc005d37e Author: Pan Li Date: Wed Aug 13 13:55:27 2025 +0800 Match: Add form 3 for unsigned SAT_MUL This patch would like to try to match the the unsigned SAT_MUL fo

[gcc r16-3347] RISC-V: Add testcase for scalar unsigned SAT_MUL form 3

https://gcc.gnu.org/g:06e6154893c974c9832821b1f3ee6c7d71bdd0a2 commit r16-3347-g06e6154893c974c9832821b1f3ee6c7d71bdd0a2 Author: Pan Li Date: Wed Aug 13 14:01:20 2025 +0800 RISC-V: Add testcase for scalar unsigned SAT_MUL form 3 Add run and asm check test cases for scalar unsigned

[gcc r16-3232] RISC-V: Update the comments of vx combine [NFC]

https://gcc.gnu.org/g:38d76a4e6033016b5e2dcaae57df67075a605edd commit r16-3232-g38d76a4e6033016b5e2dcaae57df67075a605edd Author: Pan Li Date: Sat Aug 16 16:08:23 2025 +0800 RISC-V: Update the comments of vx combine [NFC] The supported insn of vx combine is out of date, update all

[gcc r16-3231] RISC-V: Add missed DONE for vx combine pattern [NFC]

https://gcc.gnu.org/g:756f771f58f79406a08b6d574939b70d895bb613 commit r16-3231-g756f771f58f79406a08b6d574939b70d895bb613 Author: Pan Li Date: Sat Aug 16 16:01:40 2025 +0800 RISC-V: Add missed DONE for vx combine pattern [NFC] The previous patch missed the DONE indicator of the vx

[gcc r16-3168] RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:44536104696e5d665a5b598144582acb8a110002 commit r16-3168-g44536104696e5d665a5b598144582acb8a110002 Author: Pan Li Date: Mon Aug 4 09:54:34 2025 +0800 RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR cost 0, 1 and 15 Add asm dump che

[gcc r16-3167] RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on GR2VR cost

https://gcc.gnu.org/g:f1ac0f805ee25cdf0a8be73a2ef7f6e177c1b72c commit r16-3167-gf1ac0f805ee25cdf0a8be73a2ef7f6e177c1b72c Author: Pan Li Date: Mon Aug 11 21:22:08 2025 +0800 RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on GR2VR cost This patch would like to combine the ve

[gcc r16-3129] RISC-V: Add testcase for scalar unsigned SAT_MUL form 2

https://gcc.gnu.org/g:86abacb710b559a022ac61ef955457f0efe79a0a commit r16-3129-g86abacb710b559a022ac61ef955457f0efe79a0a Author: Pan Li Date: Fri Aug 1 10:46:58 2025 +0800 RISC-V: Add testcase for scalar unsigned SAT_MUL form 2 Add run and asm check test cases for scalar unsigned

[gcc r16-3128] Widening-Mul: Support unsigned scalar SAT_MUL 2

https://gcc.gnu.org/g:7d2daedde2a4ec620735d84610b05203a9cc2606 commit r16-3128-g7d2daedde2a4ec620735d84610b05203a9cc2606 Author: Pan Li Date: Fri Aug 1 10:42:23 2025 +0800 Widening-Mul: Support unsigned scalar SAT_MUL 2 For mul_overflow api, we will have PHI node similar as below:

[gcc r16-3127] Match: Add form 2 for unsigned SAT_MUL

https://gcc.gnu.org/g:deb0a4c80414697d07e808b1d2500229eb281600 commit r16-3127-gdeb0a4c80414697d07e808b1d2500229eb281600 Author: Pan Li Date: Fri Aug 1 10:37:58 2025 +0800 Match: Add form 2 for unsigned SAT_MUL This patch would like to try to match the the unsigned SAT_MUL for

[gcc r16-3126] RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost param

https://gcc.gnu.org/g:388984693487ae0626e9f24d31ebf152254a5227 commit r16-3126-g388984693487ae0626e9f24d31ebf152254a5227 Author: Pan Li Date: Wed Aug 6 22:13:26 2025 +0800 RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost param The previous cost value for vec_duplicate al

[gcc r16-2774] RISC-V: Fix scalar code-gen of unsigned SAT_MUL

https://gcc.gnu.org/g:01a784e7c5e724be3ff5ab663eb288d3ed66100b commit r16-2774-g01a784e7c5e724be3ff5ab663eb288d3ed66100b Author: Pan Li Date: Thu Jul 31 12:32:24 2025 +0800 RISC-V: Fix scalar code-gen of unsigned SAT_MUL The previous code-gen of scalar unsigned SAT_MUL, aka usmul.

[gcc r16-2686] RISC-V: Add testcases for signed avg ceil vx combine

https://gcc.gnu.org/g:9c63518f3a6a6b8c517e147db30fd47b3e371175 commit r16-2686-g9c63518f3a6a6b8c517e147db30fd47b3e371175 Author: Pan Li Date: Wed Jul 30 14:21:02 2025 +0800 RISC-V: Add testcases for signed avg ceil vx combine The unsigned avg ceil share the vaaddx.vx for the vx co

[gcc r16-2622] RISC-V: Add testcases for unsigned avg ceil vx combine.

https://gcc.gnu.org/g:7aa9565a62ea2ce04e2ddf61e1932bc123374988 commit r16-2622-g7aa9565a62ea2ce04e2ddf61e1932bc123374988 Author: Pan Li Date: Mon Jul 28 20:12:31 2025 +0800 RISC-V: Add testcases for unsigned avg ceil vx combine. The unsigned avg ceil share the vaaddux.vx for the v

[gcc r16-2605] RISC-V: Add test cases for mul based unsigned scalar SAT_MUL

https://gcc.gnu.org/g:8166458f19846fb795e31d5cf2475e0bade9f546 commit r16-2605-g8166458f19846fb795e31d5cf2475e0bade9f546 Author: Pan Li Date: Sat Jul 26 16:38:23 2025 +0800 RISC-V: Add test cases for mul based unsigned scalar SAT_MUL Add run and tree-optimized check for mul based

[gcc r16-2604] Match: Introduce mul based pattern for unsigned SAT_MUL

https://gcc.gnu.org/g:a481f299b35085bf1b218eb36a77e8a571fb7662 commit r16-2604-ga481f299b35085bf1b218eb36a77e8a571fb7662 Author: Pan Li Date: Sat Jul 26 16:32:08 2025 +0800 Match: Introduce mul based pattern for unsigned SAT_MUL Like widen_mul based pattern, we would like introduc

[gcc r16-2564] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:f9e8cf8c640f711e99802e8339578c33ae3ae1c7 commit r16-2564-gf9e8cf8c640f711e99802e8339578c33ae3ae1c7 Author: Pan Li Date: Fri Jul 25 21:28:24 2025 +0800 RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-2563] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:60289407f4fa34c339f2788b47d156a13e5b7698 commit r16-2563-g60289407f4fa34c339f2788b47d156a13e5b7698 Author: Pan Li Date: Fri Jul 25 21:26:27 2025 +0800 RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 0, 1 and 15 Add asm dump check

[gcc r16-2565] RISC-V: Add test case for vaadd.vx combine polluting VXRM

https://gcc.gnu.org/g:a5861d329a9453ba6ebd4d77c66ef44f5c8c160d commit r16-2565-ga5861d329a9453ba6ebd4d77c66ef44f5c8c160d Author: Pan Li Date: Fri Jul 25 21:29:29 2025 +0800 RISC-V: Add test case for vaadd.vx combine polluting VXRM Add asm check to make sure vx combine of vaadd.vx

[gcc r16-2562] RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost

https://gcc.gnu.org/g:b953374ec9aa39d206dbf24e7b912e4db921be12 commit r16-2562-gb953374ec9aa39d206dbf24e7b912e4db921be12 Author: Pan Li Date: Fri Jul 25 21:22:47 2025 +0800 RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-2561] RISC-V: Fix another vf FP16 combine run test failures

https://gcc.gnu.org/g:62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f commit r16-2561-g62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f Author: Pan Li Date: Fri Jul 25 22:11:13 2025 +0800 RISC-V: Fix another vf FP16 combine run test failures Like Robin's fix for vf combine f16.c run tests, there

[gcc r16-2461] RISC-V: Add test case for vx combine polluting VXRM

https://gcc.gnu.org/g:198653e1cc4ddd33a837bd7130b7c347b27202a6 commit r16-2461-g198653e1cc4ddd33a837bd7130b7c347b27202a6 Author: Pan Li Date: Wed Jul 23 13:02:55 2025 +0800 RISC-V: Add test case for vx combine polluting VXRM Add asm check to make sure vx combine of vaaddu.vx will

[gcc r16-2460] RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr

https://gcc.gnu.org/g:5aec85a5f490895f90c1ef75f965ea100e80f50e commit r16-2460-g5aec85a5f490895f90c1ef75f965ea100e80f50e Author: Pan Li Date: Wed Jul 23 12:08:02 2025 +0800 RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr The vaaddu.vx combine almost comes from avg_floor,

[gcc r16-2387] RISC-V: Allow VLS DImode for sat_op vx DImode pattern

https://gcc.gnu.org/g:e184f73d91b437ba46e5eaf1817db6b182097627 commit r16-2387-ge184f73d91b437ba46e5eaf1817db6b182097627 Author: Pan Li Date: Mon Jul 21 09:20:46 2025 +0800 RISC-V: Allow VLS DImode for sat_op vx DImode pattern When try to introduce the vaaddu.vx combine for DImode

[gcc r16-2386] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI

https://gcc.gnu.org/g:2d90c95f77a000410fdf781adf4c312dcf7d98cf commit r16-2386-g2d90c95f77a000410fdf781adf4c312dcf7d98cf Author: Pan Li Date: Mon Jul 21 09:16:17 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI and SI mode

[gcc r16-2385] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI

https://gcc.gnu.org/g:04cfb71957473c3c738e2900940a6781a3f0544d commit r16-2385-g04cfb71957473c3c738e2900940a6781a3f0544d Author: Pan Li Date: Mon Jul 21 09:13:27 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI and SI mode

[gcc r16-2388] RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode

https://gcc.gnu.org/g:bd9fc3a53ff91b846b5999a91438f835e1ed64f5 commit r16-2388-gbd9fc3a53ff91b846b5999a91438f835e1ed64f5 Author: Pan Li Date: Mon Jul 21 09:28:06 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode Add asm dump check and run test for vec_du

[gcc r16-2384] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode

https://gcc.gnu.org/g:9e2aaaba47cf635169e9051c4e86f39d04c69f1d commit r16-2384-g9e2aaaba47cf635169e9051c4e86f39d04c69f1d Author: Pan Li Date: Mon Jul 21 09:06:52 2025 +0800 RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode This patch woul

[gcc r16-2365] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC]

https://gcc.gnu.org/g:1e77645795fdf25ffdb5e9931fd9c946f2261fe2 commit r16-2365-g1e77645795fdf25ffdb5e9931fd9c946f2261fe2 Author: Pan Li Date: Sat Jul 19 10:49:15 2025 +0800 RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] The previous test case doesn't leverage

[gcc r16-2364] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil

https://gcc.gnu.org/g:c655047d3dbd4db295ea9385ac2e337cba0b5e05 commit r16-2364-gc655047d3dbd4db295ea9385ac2e337cba0b5e05 Author: Pan Li Date: Sat Jul 19 17:17:11 2025 +0800 RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil According to the semantics of the avg_floor

[gcc r16-2351] RISC-V: Support RVVDImode for avg3_ceil auto vect

https://gcc.gnu.org/g:c1a34e80991c85d02af6be3edb4f8c4e1116e363 commit r16-2351-gc1a34e80991c85d02af6be3edb4f8c4e1116e363 Author: Pan Li Date: Wed Jul 16 21:40:14 2025 +0800 RISC-V: Support RVVDImode for avg3_ceil auto vect Like the avg3_floor pattern, the avg3_ceil has the sim

[gcc r16-2277] RISC-V: Support RVVDImode for avg3_floor auto vect

https://gcc.gnu.org/g:430be3b933bfac1f1caace4f0ef393a4d434ea0f commit r16-2277-g430be3b933bfac1f1caace4f0ef393a4d434ea0f Author: Pan Li Date: Tue Jul 15 09:45:05 2025 +0800 RISC-V: Support RVVDImode for avg3_floor auto vect The avg3_floor pattern leverage the add and shift rtl

[gcc r16-2235] RISC-V: Add testcase for rv32 SAT_MUL from uint64

https://gcc.gnu.org/g:f7f0539ae9c7fbd33c29c6e73b6970d85b7394b7 commit r16-2235-gf7f0539ae9c7fbd33c29c6e73b6970d85b7394b7 Author: Pan Li Date: Fri Jul 11 08:58:31 2025 +0800 RISC-V: Add testcase for rv32 SAT_MUL from uint64 Add the run and asm testcase for rv32 SAT_MUL, widen mul f

[gcc r16-2234] Match: Refine the widen mul check for SAT_MUL pattern

https://gcc.gnu.org/g:f01216a0b71a3e88c796ed302d6a6bc2fdb35d44 commit r16-2234-gf01216a0b71a3e88c796ed302d6a6bc2fdb35d44 Author: Pan Li Date: Fri Jul 11 08:38:09 2025 +0800 Match: Refine the widen mul check for SAT_MUL pattern The widen mul will have source type from N-bits to

[gcc r16-2157] RISCV: Remove the v extension requirement for sat scalar run test

https://gcc.gnu.org/g:e3d1b3cce876630380e6c2e3782c2fb0f4e7fb42 commit r16-2157-ge3d1b3cce876630380e6c2e3782c2fb0f4e7fb42 Author: Pan Li Date: Wed Jul 9 10:40:52 2025 +0800 RISCV: Remove the v extension requirement for sat scalar run test The sat scalar run test should not require

[gcc r16-2140] RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost

https://gcc.gnu.org/g:8877ab269e1408522839377c3ef725efe1589277 commit r16-2140-g8877ab269e1408522839377c3ef725efe1589277 Author: Pan Li Date: Mon Jul 7 11:07:11 2025 +0800 RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-2142] RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:503e1680ccaffbc90b394191a2bc1ac88b1d113f commit r16-2142-g503e1680ccaffbc90b394191a2bc1ac88b1d113f Author: Pan Li Date: Mon Jul 7 11:17:00 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-2141] RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:e8bb09a0050046082204eb28b26ecf1594edc2d0 commit r16-2141-ge8bb09a0050046082204eb28b26ecf1594edc2d0 Author: Pan Li Date: Mon Jul 7 11:13:15 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-2117] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

https://gcc.gnu.org/g:a09b415b87cd98e3a4f3e197ad4e9e67a335c1d4 commit r16-2117-ga09b415b87cd98e3a4f3e197ad4e9e67a335c1d4 Author: Pan Li Date: Tue Jul 8 10:46:29 2025 +0800 RISC-V: Disable uint128_t testcase of SAT_MUL when rv32 The rv32 doesn't support __uint128, and then we will

[gcc r16-2061] RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:65c40c0211f01579d1e7f259271cb79a8a19d533 commit r16-2061-g65c40c0211f01579d1e7f259271cb79a8a19d533 Author: Pan Li Date: Wed Jul 2 10:52:25 2025 +0800 RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t Add run and tree-optimized check for unsign

[gcc r16-2060] RISC-V: Implement unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:62b99e84b886fbdd70118cc260ae0f2516c2f3f5 commit r16-2060-g62b99e84b886fbdd70118cc260ae0f2516c2f3f5 Author: Pan Li Date: Wed Jul 2 10:35:10 2025 +0800 RISC-V: Implement unsigned scalar SAT_MUL from uint128_t This patch would like to implement the SAT_MUL scala

[gcc r16-2059] Widening-Mul: Support unsigned scalar SAT_MUL form 1

https://gcc.gnu.org/g:dc30f404170f538af6bf2457ccff252b08302dec commit r16-2059-gdc30f404170f538af6bf2457ccff252b08302dec Author: Pan Li Date: Wed Jul 2 09:59:26 2025 +0800 Widening-Mul: Support unsigned scalar SAT_MUL form 1 This patch would like to try to match the SAT_MUL during

[gcc r16-2058] Internal-fn: Introduce new IFN_SAT_MUL for unsigned int

https://gcc.gnu.org/g:35f5a18872127e18aadcbbc08df7885974280c79 commit r16-2058-g35f5a18872127e18aadcbbc08df7885974280c79 Author: Pan Li Date: Wed Jul 2 09:46:08 2025 +0800 Internal-fn: Introduce new IFN_SAT_MUL for unsigned int This patch would like to add the middle-end presentat

[gcc r16-2023] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:2f19d9408477829ab7de465310fa0068be0f43ff commit r16-2023-g2f19d9408477829ab7de465310fa0068be0f43ff Author: Pan Li Date: Thu Jul 3 17:17:28 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-2022] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:ea86a5a111f3bc883035b0783fe419e5bd2722a0 commit r16-2022-gea86a5a111f3bc883035b0783fe419e5bd2722a0 Author: Pan Li Date: Thu Jul 3 17:16:21 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-2021] RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost

https://gcc.gnu.org/g:0601f461649323c7d6c7bb33c6839f60949116c2 commit r16-2021-g0601f461649323c7d6c7bb33c6839f60949116c2 Author: Pan Li Date: Thu Jul 3 17:07:44 2025 +0800 RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-1823] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

https://gcc.gnu.org/g:b7fe719e449db56d665da17ca4f4ba7977da34ed commit r16-1823-gb7fe719e449db56d665da17ca4f4ba7977da34ed Author: Pan Li Date: Fri Jun 27 09:02:03 2025 +0800 RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost This patch would like to combine the ve

[gcc r16-1826] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:ff87aefc061d7de3b233bfe034fb29cc253f77a9 commit r16-1826-gff87aefc061d7de3b233bfe034fb29cc253f77a9 Author: Pan Li Date: Fri Jun 27 09:09:08 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1825] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:342694acd59c87f35d97805609ba54f547b52881 commit r16-1825-g342694acd59c87f35d97805609ba54f547b52881 Author: Pan Li Date: Fri Jun 27 09:06:38 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump chec

[gcc r16-1824] RISC-V: Reconcile the existing test due to cost model change

https://gcc.gnu.org/g:db267b0d1dcabd09d9064093383e38f2596345a4 commit r16-1824-gdb267b0d1dcabd09d9064093383e38f2596345a4 Author: Pan Li Date: Fri Jun 27 11:35:18 2025 +0800 RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cos

[gcc r16-1629] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:11811e698b460b5fe45777f4c333aa74655cff39 commit r16-1629-g11811e698b460b5fe45777f4c333aa74655cff39 Author: Pan Li Date: Sat Jun 21 10:07:38 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1628] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:9a8f82d6a63e36ffba883b365101b58955ca7c64 commit r16-1628-g9a8f82d6a63e36ffba883b365101b58955ca7c64 Author: Pan Li Date: Sat Jun 21 09:10:07 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump chec

[gcc r16-1627] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

https://gcc.gnu.org/g:a2d018b642019165511e89d47bfb46af55f81f98 commit r16-1627-ga2d018b642019165511e89d47bfb46af55f81f98 Author: Pan Li Date: Sat Jun 21 09:00:16 2025 +0800 RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost This patch would like to combine the ve

[gcc r16-1597] RISC-V: Fix ICE for expand_select_vldi [PR120652]

https://gcc.gnu.org/g:52582b40a9bf839ae3771de1557ce6691eb8eedd commit r16-1597-g52582b40a9bf839ae3771de1557ce6691eb8eedd Author: Pan Li Date: Thu Jun 19 18:58:17 2025 +0800 RISC-V: Fix ICE for expand_select_vldi [PR120652] The will be one ICE when expand pass, the bt similar as be

[gcc r16-1583] RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:89ec7ba1b1815aa9ba68d17f01e1b5a4dc20bde5 commit r16-1583-g89ec7ba1b1815aa9ba68d17f01e1b5a4dc20bde5 Author: Pan Li Date: Thu Jun 19 10:49:07 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1582] RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:289220af97f712d253d0b9d649e57e7da3dd37ea commit r16-1582-g289220af97f712d253d0b9d649e57e7da3dd37ea Author: Pan Li Date: Thu Jun 19 10:47:33 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1581] RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost

https://gcc.gnu.org/g:7ea9105f2609efe089461d7e92533324eb5b1103 commit r16-1581-g7ea9105f2609efe089461d7e92533324eb5b1103 Author: Pan Li Date: Thu Jun 19 10:44:14 2025 +0800 RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-1553] RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:29da9a40d1a1e21808dc596e3535058231004492 commit r16-1553-g29da9a40d1a1e21808dc596e3535058231004492 Author: Pan Li Date: Tue Jun 17 10:05:33 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1554] RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:a0ffc9b1bfd45da5ce676a0cef419381c021f54b commit r16-1554-ga0ffc9b1bfd45da5ce676a0cef419381c021f54b Author: Pan Li Date: Tue Jun 17 10:08:44 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-1552] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost

https://gcc.gnu.org/g:13c0ad1611eae7f0cd2a412b2f549a368d7d8be2 commit r16-1552-g13c0ad1611eae7f0cd2a412b2f549a368d7d8be2 Author: Pan Li Date: Tue Jun 17 10:00:54 2025 +0800 RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost This patch would like to combine the vec_du

[gcc r16-1526] RISC-V: Refine VX combine test case 0 to avoid code duplication

https://gcc.gnu.org/g:ad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990 commit r16-1526-gad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990 Author: Pan Li Date: Sun Jun 15 16:28:38 2025 +0800 RISC-V: Refine VX combine test case 0 to avoid code duplication The case 0 for vx combine def functions are

[gcc r16-1514] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:50034d8f109a4d40c5bd63b63d8e8c8d3ea69e56 commit r16-1514-g50034d8f109a4d40c5bd63b63d8e8c8d3ea69e56 Author: Pan Li Date: Sat Jun 14 22:32:23 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1515] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:afe3401f2e73e21d0e54ea8529642e37ae4a23d5 commit r16-1515-gafe3401f2e73e21d0e54ea8529642e37ae4a23d5 Author: Pan Li Date: Sat Jun 14 22:34:36 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1513] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

https://gcc.gnu.org/g:7f153b96aa84773e7b18cf66db73afab55850c2a commit r16-1513-g7f153b96aa84773e7b18cf66db73afab55850c2a Author: Pan Li Date: Sat Jun 14 22:29:40 2025 +0800 RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-1477] RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR cost

https://gcc.gnu.org/g:55e9547b87c60d5807e24a80e79a0d219ac12d9c commit r16-1477-g55e9547b87c60d5807e24a80e79a0d219ac12d9c Author: Pan Li Date: Wed Jun 11 21:49:21 2025 +0800 RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR cost This patch would like to combine the vec_du

[gcc r16-1481] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:f3001dd5fe57738be222c3af690f7fdd86f531a1 commit r16-1481-gf3001dd5fe57738be222c3af690f7fdd86f531a1 Author: Pan Li Date: Thu Jun 12 10:42:39 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2 Add asm dum

[gcc r16-1479] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2ae6cd8cd19962441403e5975d15f0fd14d662e2 commit r16-1479-g2ae6cd8cd19962441403e5975d15f0fd14d662e2 Author: Pan Li Date: Thu Jun 12 09:12:09 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15 Add asm du

[gcc r16-1480] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:86d1b55da654c05343279a54ffe2cbcc0cbebb21 commit r16-1480-g86d1b55da654c05343279a54ffe2cbcc0cbebb21 Author: Pan Li Date: Thu Jun 12 10:23:49 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2 Add asm dum

[gcc r16-1478] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2ebb805fe2f29262a455aaf412b3f77060e05fe2 commit r16-1478-g2ebb805fe2f29262a455aaf412b3f77060e05fe2 Author: Pan Li Date: Wed Jun 11 21:51:08 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15 Add asm du

[gcc r16-1359] RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:bcabb6b0c707271b86a59be755f295ab7c125df1 commit r16-1359-gbcabb6b0c707271b86a59be755f295ab7c125df1 Author: Pan Li Date: Mon Jun 9 16:35:47 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-1358] RISC-V: Add test for vec_duplicate + vremu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:0bdea31036e8268edd1b4ea3ed07478c07c96ad1 commit r16-1358-g0bdea31036e8268edd1b4ea3ed07478c07c96ad1 Author: Pan Li Date: Mon Jun 9 16:33:52 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1357] RISC-V: Reconcile the existing test for vremu.vx combine

https://gcc.gnu.org/g:b59354cf309052de6a1c297f06411691c03bfd24 commit r16-1357-gb59354cf309052de6a1c297f06411691c03bfd24 Author: Pan Li Date: Mon Jun 9 16:28:50 2025 +0800 RISC-V: Reconcile the existing test for vremu.vx combine Some existing vrem related test need some adjust for

[gcc r16-1356] RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost

https://gcc.gnu.org/g:85de2b8b58e1644f6d5f0f182426122416b19e6f commit r16-1356-g85de2b8b58e1644f6d5f0f182426122416b19e6f Author: Pan Li Date: Mon Jun 9 16:24:34 2025 +0800 RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-1296] RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:daee1935f4e366c09fc085905cb49bbf264c5663 commit r16-1296-gdaee1935f4e366c09fc085905cb49bbf264c5663 Author: Pan Li Date: Sun Jun 8 16:53:05 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-1295] RISC-V: Reconcile the existing test for vrem.vx combine

https://gcc.gnu.org/g:4df4acf002cc3672478edb43f374cef3ffbd1f54 commit r16-1295-g4df4acf002cc3672478edb43f374cef3ffbd1f54 Author: Pan Li Date: Sun Jun 8 16:50:52 2025 +0800 RISC-V: Reconcile the existing test for vrem.vx combine Some existing vrem related test need some adjust for

[gcc r16-1297] RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:8d745f6d70172132a594dcc650a6d489e7246eda commit r16-1297-g8d745f6d70172132a594dcc650a6d489e7246eda Author: Pan Li Date: Sun Jun 8 16:55:34 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-1294] RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost

https://gcc.gnu.org/g:b96e319dbd19328a2243b2950155be57532c213b commit r16-1294-gb96e319dbd19328a2243b2950155be57532c213b Author: Pan Li Date: Sun Jun 8 16:48:33 2025 +0800 RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-1257] RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:c01830fa809fa18d1d54b29a89cb65f3bb8f5676 commit r16-1257-gc01830fa809fa18d1d54b29a89cb65f3bb8f5676 Author: Pan Li Date: Fri Jun 6 09:51:10 2025 +0800 RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-1256] RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2ca7622fd7b32fd538edea8fd8bd8b97ba07ef16 commit r16-1256-g2ca7622fd7b32fd538edea8fd8bd8b97ba07ef16 Author: Pan Li Date: Fri Jun 6 09:49:56 2025 +0800 RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1255] RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost

https://gcc.gnu.org/g:be205ec675ed79275e694dda90f0f97fc6ac0e7a commit r16-1255-gbe205ec675ed79275e694dda90f0f97fc6ac0e7a Author: Pan Li Date: Fri Jun 6 09:33:21 2025 +0800 RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-1258] RISC-V: Reconcile the existing test for vdivu.vx combine

https://gcc.gnu.org/g:08a0b6dabd76c8ca4366a59c2fdcd1ef8f8b1cb9 commit r16-1258-g08a0b6dabd76c8ca4366a59c2fdcd1ef8f8b1cb9 Author: Pan Li Date: Fri Jun 6 10:03:50 2025 +0800 RISC-V: Reconcile the existing test for vdivu.vx combine Some existing vdiv related test need some adjust for

[gcc r16-1182] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

https://gcc.gnu.org/g:8cf31de8c8fec295c5f627b399d9e015df266297 commit r16-1182-g8cf31de8c8fec295c5f627b399d9e015df266297 Author: Pan Li Date: Thu Jun 5 11:04:33 2025 +0800 RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv The div of rvv has not such insn v2 = div (vec_dup

[gcc r16-1098] RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC]

https://gcc.gnu.org/g:a8b38447efe2c74094b865e1cc44723659dac2e4 commit r16-1098-ga8b38447efe2c74094b865e1cc44723659dac2e4 Author: Pan Li Date: Wed Jun 4 11:06:52 2025 +0800 RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC] Some similar code could be wrapped to fun

[gcc r16-1080] RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost

https://gcc.gnu.org/g:451737734b8913c5de8cfe597d5d20477af6c5ef commit r16-1080-g451737734b8913c5de8cfe597d5d20477af6c5ef Author: Pan Li Date: Mon Jun 2 16:56:59 2025 +0800 RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-1083] RISC-V: Reconcile the existing test for vdiv.vx combine

https://gcc.gnu.org/g:4c2d94aed41778226ae08c718459eed5ee65d455 commit r16-1083-g4c2d94aed41778226ae08c718459eed5ee65d455 Author: Pan Li Date: Mon Jun 2 21:21:18 2025 +0800 RISC-V: Reconcile the existing test for vdiv.vx combine Some existing vdiv related test need some adjust for

[gcc r16-1081] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:a5222407c993c01dcce53590c5fa799f7a927b4f commit r16-1081-ga5222407c993c01dcce53590c5fa799f7a927b4f Author: Pan Li Date: Mon Jun 2 17:01:27 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-1082] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:661c7377df05010ffae8a81c17b3870f8d927608 commit r16-1082-g661c7377df05010ffae8a81c17b3870f8d927608 Author: Pan Li Date: Mon Jun 2 17:03:02 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-1034] RISC-V: Fix line too long format issue for autovect.md [NFC]

https://gcc.gnu.org/g:c33ad4f3f2a652fcd07d249736b6c5233fa1da8e commit r16-1034-gc33ad4f3f2a652fcd07d249736b6c5233fa1da8e Author: Pan Li Date: Sat May 31 11:01:06 2025 +0800 RISC-V: Fix line too long format issue for autovect.md [NFC] Inspired by the avg_ceil patches, notice there

[gcc r16-1015] RISC-V: Add test cases for avg_ceil vaadd implementation

https://gcc.gnu.org/g:72972bc3a1b35bcfc83d801a9da45121210bc3c3 commit r16-1015-g72972bc3a1b35bcfc83d801a9da45121210bc3c3 Author: Pan Li Date: Thu May 29 21:33:44 2025 +0800 RISC-V: Add test cases for avg_ceil vaadd implementation Add asm and run testcase for avg_ceil vaadd impleme

[gcc r16-1014] RISC-V: Reconcile the existing test for avg_ceil

https://gcc.gnu.org/g:6d4c38b232e1d58c85de7959411cc1562a7a0bdc commit r16-1014-g6d4c38b232e1d58c85de7959411cc1562a7a0bdc Author: Pan Li Date: Thu May 29 21:31:54 2025 +0800 RISC-V: Reconcile the existing test for avg_ceil Some existing avg_floor test need updated due to change to

[gcc r16-1013] RISC-V: Leverage vaadd.vv for signed standard name avg_ceil

https://gcc.gnu.org/g:6bcd522438250d014d0fa1e4bcf2aa049934c887 commit r16-1013-g6bcd522438250d014d0fa1e4bcf2aa049934c887 Author: Pan Li Date: Thu May 29 21:19:36 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_ceil The avg_ceil has the rounding mode towards +inf,

[gcc r16-947] RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:663cb52b0e8df70830a8def86a5254a59d373732 commit r16-947-g663cb52b0e8df70830a8def86a5254a59d373732 Author: Pan Li Date: Wed May 28 16:22:04 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-946] RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b36bde2fc5cc7048f294adee45fb9a0be0092d13 commit r16-946-gb36bde2fc5cc7048f294adee45fb9a0be0092d13 Author: Pan Li Date: Wed May 28 16:20:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-945] RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost

https://gcc.gnu.org/g:2e4267a6fe143bd72376653812f59f343cb1c101 commit r16-945-g2e4267a6fe143bd72376653812f59f343cb1c101 Author: Pan Li Date: Wed May 28 16:16:49 2025 +0800 RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost This patch would like to combine the vec_dup

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