Re: [PATCH, vec-tails 03/10] Support epilogues vectorization with no masking

On 06/15/2016 05:03 AM, Richard Biener wrote: On Thu, May 19, 2016 at 9:39 PM, Ilya Enkovich wrote: Hi, This patch introduces changes required to run vectorizer on loop epilogue. This also enables epilogue vectorization using a vector of smaller size. While the idea

Re: [PATCH, vec-tails 02/10] Extend _loop_vec_info structure with epilogue related fields

On 05/19/2016 01:38 PM, Ilya Enkovich wrote: Hi, This patch adds new fields to _loop_vec_info structure to support loop epilogue vectorization. Thanks, Ilya -- gcc/ 2016-05-19 Ilya Enkovich * tree-vectorizer.h (struct _loop_vec_info): Add new fields

Re: [PATCH, vec-tails 01/10] New compiler options

On 05/20/2016 05:40 AM, Ilya Enkovich wrote: 2016-05-20 14:17 GMT+03:00 Richard Biener : On Fri, May 20, 2016 at 11:50 AM, Ilya Enkovich wrote: 2016-05-20 12:26 GMT+03:00 Richard Biener : On Thu, May 19, 2016 at

Re: [RFC][PATCH, vec-tails 00/10] Support vectorization of loop epilogues

On 06/15/2016 06:05 AM, Richard Biener wrote: So I've gone over the patches and gave mostly high-level comments. The vectorizer is already in somewhat messy (aka not easy to follow) state, this series doesn't improve the situation (heh). Esp. the high-level structure for code generation and its

Re: [PATCH] Fix up CSE handling of const/pure calls (PR rtl-optimization/71532)

On 06/15/2016 07:14 PM, Alan Modra wrote: On Wed, Jun 15, 2016 at 04:03:04PM -0600, Jeff Law wrote: FWIW I don't think ownership of the argument slots has ever been definitively addressed by any ABI and it's been an open question in my mind for 20+ years -- though I've largely leaned towards

[PATCH,openacc] check for compatible loop parallelism with acc routine calls

This patch addresses the following problems with acc routines: * incorrectly permitting 'acc seq' loops to call gang, worker and vector routines * lto-wrapper errors when a function or subroutine isn't marked as 'acc routine' The solution to the first problem is straightforward. It only

Re: [C++ PATCH] Don't promote bitfields in last arg of __builtin_*_overflow_p

On 06/15/2016 01:51 PM, Jakub Jelinek wrote: On Wed, Jun 15, 2016 at 08:08:22AM -0600, Martin Sebor wrote: I like the idea of being able to use the built-ins for this, but I think it would be confusing for them to follow subtly different rules for C than for C++. Since the value of the last

Re: [PATCH, ping] zero-length arrays in OpenACC

Ping. Cesar On 06/01/2016 02:35 PM, Cesar Philippidis wrote: > This patch teaches c and c++ front ends and omp-low how to deal with > subarray involving GOMP_MAP_FORCE_{PRESENT,TO,FROM,TOFROM} data > mappings. As the libgomp test case shows, it might be possible for a > subarray to have zero

Re: [PATCH] Fix up CSE handling of const/pure calls (PR rtl-optimization/71532)

On Wed, Jun 15, 2016 at 04:03:04PM -0600, Jeff Law wrote: > FWIW I don't think ownership of the argument slots has ever been > definitively addressed by any ABI and it's been an open question in my mind > for 20+ years -- though I've largely leaned towards callee ownership on my > own thinking.

Re: [PATCH] Backport PowerPC complex __float128 compiler support to GCC 6.x

On Wed, Jun 15, 2016 at 03:12:55PM +0200, Richard Biener wrote: > On Wed, 15 Jun 2016, Michael Meissner wrote: > > Eventually, I decided to punt having to have explicit paths for widening. I > > used fractional modes for IFmode (ibm long double format) and KFmode (IEEE > > 128-bit format).

Re: [PATCH] Add port for Phoenix-RTOS on ARM platform.

On 06/15/2016 08:21 AM, Jakub Sejdak wrote: Hello, First of all, do you or your employer have a copyright assignment to the FSF? The above link contains instructions on how to do that. It is a necessary prerequisite to accepting any non-small change. Sorry for a late response, but it took me

Re: [PATCH] Fix up CSE handling of const/pure calls (PR rtl-optimization/71532)

On 06/15/2016 01:46 PM, Jakub Jelinek wrote: Hi! As the following testcase shows, CSE mishandles const/pure calls, it assumes that const/pure calls can't clobber even their argument slots. But, the argument slots are owned by the callee, so need to be volatile across the calls. On the

Re: [PATCH][vectorizer][2/2] Hook up mult synthesis logic into vectorisation of mult-by-constant

On Wed, 15 Jun 2016, Kyrill Tkachov wrote: This is a respin of https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00952.html following feedback. I've changed the code to cast the operand to an unsigned type before applying the multiplication algorithm and cast it back to the signed type at the

Re: [PATCH], PowerPC: Allow DImode in Altivec registers

On Wed, Jun 15, 2016 at 02:51:20PM -0500, Segher Boessenkool wrote: > On Wed, Jun 15, 2016 at 02:24:41PM -0400, Michael Meissner wrote: > > > > ; Some DImode loads are best done as a load of -1 followed by a mask > > > > ; instruction. > > > > (define_split > > > > - [(set (match_operand:DI 0

Re: [PATCH] Fix builtin-arith-overflow-p-1[23].c on i686

On Wed, Jun 15, 2016 at 9:57 PM, Jakub Jelinek wrote: > Hi! > > On the builtin-arith-overflow-p-1{2,3}.c testcases (posted earlier today) > i?86 miscompiles e.g. t111_4mul function. Before peephole2 we have: > (insn 9 6 50 2 (parallel [ > (set (reg:CCO 17 flags) >

Re: [C++ Patch] Avoid a few more '+' in warnings

Yep, that looks obvious. Jason

[C++ Patch] Avoid a few more '+' in warnings

Hi, looks like last year I forgot to grep for %q+F and %q+#F. Tested x86_64-linux. Should be obvious... Thanks, Paolo. // 2016-06-15 Paolo Carlini * decl.c (wrapup_globals_for_namespace): Use DECL_SOURCE_LOCATION and "%qF" in

[PATCH] Fix builtin-arith-overflow-p-1[23].c on i686

Hi! On the builtin-arith-overflow-p-1{2,3}.c testcases (posted earlier today) i?86 miscompiles e.g. t111_4mul function. Before peephole2 we have: (insn 9 6 50 2 (parallel [ (set (reg:CCO 17 flags) (eq:CCO (mult:DI (sign_extend:DI (reg/v:SI 0 ax [orig:90 x ] [90]))

[C++ PATCH] Don't promote bitfields in last arg of __builtin_*_overflow_p

On Wed, Jun 15, 2016 at 08:08:22AM -0600, Martin Sebor wrote: > I like the idea of being able to use the built-ins for this, but > I think it would be confusing for them to follow subtly different > rules for C than for C++. Since the value of the last argument Here is incremental patch to the

Re: [PATCH], PowerPC: Allow DImode in Altivec registers

On Wed, Jun 15, 2016 at 02:24:41PM -0400, Michael Meissner wrote: > > > ; Some DImode loads are best done as a load of -1 followed by a mask > > > ; instruction. > > > (define_split > > > - [(set (match_operand:DI 0 "gpc_reg_operand") > > > + [(set (match_operand:DI 0

[C++ PATCH] Fix some DECL_BUILT_IN uses in C++ FE

Hi! I've noticed 3 spots in the C++ FE test just DECL_BUILT_IN and then immediately compare DECL_FUNCTION_CODE against BUILT_IN_* constants. That is only meaningful for BUILT_IN_NORMAL, while DECL_BUILT_IN macro is DECL_BUILT_IN_CLASS != NOT_BUILT_IN, so it also e.g. includes BUILT_IN_MD. If

[PATCH] Fix up CSE handling of const/pure calls (PR rtl-optimization/71532)

Hi! As the following testcase shows, CSE mishandles const/pure calls, it assumes that const/pure calls can't clobber even their argument slots. But, the argument slots are owned by the callee, so need to be volatile across the calls. On the testcase the second round of argument stores is

RE: [PATCH][AArch64] Enable -frename-registers at -O2 and higher

> On Fri, May 27, 2016 at 02:50:15PM +0100, Kyrill Tkachov wrote: > > > > As mentioned in > > https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00297.html, > > frename-registers registers can be beneficial for aarch64 and the > > patch at https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01618.html > >

Re: [PATCH] Allow fwprop to undo vectorization harm (PR68961)

Richard Biener writes: > With the proposed cost change for vector construction we will end up > vectorizing the testcase in PR68961 again (on x86_64 and likely > on ppc64le as well after that target gets adjustments). Currently > we can't optimize that away again noticing the

Re: [PATCH], PowerPC: Allow DImode in Altivec registers

On Tue, Jun 14, 2016 at 05:53:46PM -0500, Segher Boessenkool wrote: > On Mon, Jun 13, 2016 at 02:29:41PM -0400, Michael Meissner wrote: > > It would help if I included the patch. > > :-) > > > > Are these changes ok to install in the trunk? Assuming they go in the > > > trunk, > > > can I

Re: [PATCH 2/2] gcc/genrecog: Don't warn for missing mode on special predicates

Andrew Burgess writes: > In md.texi it says: > > Predicates written with @code{define_special_predicate} do not get any > automatic mode checks, and are treated as having special mode handling > by @command{genrecog}. > > However, in genrecog, when validating a

Re: [Patch] Implement is_[nothrow_]swappable (p0185r1) - 2nd try

2016-06-14 23:22 GMT+02:00 Daniel Krügler : > This is an implementation of the Standard is_swappable traits according to > > http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0185r1.html > > During that work it has been found that std::array's member swap's

Re: Cilk Plus testsuite needs massive cleanup (PR testsuite/70595)

On Jun 14, 2016, at 11:09 AM, Ilya Verbin wrote: > > On Fri, Apr 29, 2016 at 11:19:47 -0700, Mike Stump wrote: >> On Apr 29, 2016, at 5:41 AM, Rainer Orth >> wrote: >>> diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h >>> ---

Re: [Patch, cfg] Improve jump to return optimization for complex return

Segher Boessenkool writes: > On Tue, Jun 14, 2016 at 03:53:59PM +0100, Jiong Wang wrote: >> "bl to pop" into "pop" which is "jump to return" into "return", so a better >> place to fix this issue is at try_optimize_cfg where we are doing these >> jump/return optimization already: >> >> /* Try

Re: [C++ PATCH] Add testcase for 4.8 bug

OK. Jason

Re: [patch, avr] Fix PR67353

2016-06-15 13:19 GMT+03:00 Pitchumani Sivanupandi : > On Mon, 2016-06-13 at 17:48 +0200, Georg-Johann Lay wrote: >> Pitchumani Sivanupandi schrieb: >> > >> > $ avr-gcc test.c -Wno-misspelled-isr >> > $ >> What about -Werror=misspelled-isr? > > Updated patch. > >>

Re: [patch,avr] ad PR71103: also handle QImode SUBREGs of CONST

2016-06-15 12:11 GMT+03:00 Georg-Johann Lay : > This patch handles the cases when subreg:QI of a CONST or LABEL_REF is to be > moved to a QImode register. The original patch only handled SYMBOL_REFs. > > OK for trunk and backport? > > > Johann > > -- > > gcc/ > PR

Re: [PATCH][AArch64][obvious] Clean up parentheses and use GET_MODE_UNIT_BITSIZE in a couple of patterns

On 15/06/16 17:12, Andreas Schwab wrote: Kyrill Tkachov writes: diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 6effd7d42d18c9b526aaaec93a44e8801908e164..a19d1711b5bcb516e4aca6a22d1b79df4f32923f 100644 ---

Re: [PATCH][AArch64][obvious] Clean up parentheses and use GET_MODE_UNIT_BITSIZE in a couple of patterns

Kyrill Tkachov writes: > diff --git a/gcc/config/aarch64/aarch64-simd.md > b/gcc/config/aarch64/aarch64-simd.md > index > 6effd7d42d18c9b526aaaec93a44e8801908e164..a19d1711b5bcb516e4aca6a22d1b79df4f32923f > 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++

[PATCH][AArch64][obvious] Clean up parentheses and use GET_MODE_UNIT_BITSIZE in a couple of patterns

Hi all, The parentheses in these two patterns are a bit of a mess and we can remove them. Do that. also, use '{' and '}' for the C code so that we can avoid escaping the strings in the block. Also, use GET_MODE_UNIT_BITSIZE directly instead of taking GET_MODE_UNIT_SIZE and multiplying by

[PATCH, CHKP, PR middle-end/71529] Fix DECL_CONTEXT for args of instrumentation clones with no body

Hi, Currently chkp_build_instrumented_fndecl copies arguments list in case function has no body. Copied arguments have incorrect DECL_CONTEXT and this patch fixes it. Bootstrapped and regtested for x86_64-unknown-linux-gnu. I'm going to commit it to trunk and later port to gcc-6-branch.

Re: [PATCH] PR 71483 - Fix live SLP operations

On June 14, 2016 4:14:20 PM GMT+02:00, Alan Hayward wrote: >In the given testcase, g++ splits a live operation into two scalar >statements >and four vector statements. > >_5 = _4 >> 2; > _7 = (short int) _5; > >Is turned into: > >vect__5.32_80 = vect__4.31_76 >> 2; >

Re: [PATCH] Optimize inserting value_type into std::vector

On 15/06/16 11:34 +0100, Jonathan Wakely wrote: On 15/06/16 11:15 +0100, Jonathan Wakely wrote: * include/bits/stl_vector.h (vector::_S_insert_aux_assign): Define new overloaded functions. * include/bits/vector.tcc (vector::_M_insert_aux): Use new functions to

Re: [PATCH] PR71275 ira.c bb_loop_depth

On Wed, Jun 15, 2016 at 7:06 AM, Bernd Schmidt wrote: > > > On 06/15/2016 04:03 PM, Alan Modra wrote: >> >> On Wed, Jun 15, 2016 at 11:49:50AM +0200, Bernd Schmidt wrote: >>> >>> On 06/15/2016 03:30 AM, Alan Modra wrote: Between these two calls to

[PATCH] [OBVIOUS] Fix obvious typo in predict.c

Hello. This corrects a typo in predict.c, which is pre-approved by Honza. Survives regression tests & bootstraps on x86_64-linux-gnu. Installed as r237481. Martin >From 5d755d1a83094b24319d4a31d1c951c8aa622a87 Mon Sep 17 00:00:00 2001 From: marxin Date: Wed, 15 Jun 2016

Re: [PATCH, i386]: Implement PR 71246, Missing built-in functions for float128 NaNs

On Tue, Jun 14, 2016 at 11:45 PM, Rainer Orth wrote: > Uros Bizjak writes: > >> testsuite/ChangeLog: >> >> 2016-06-12 Uros Bizjak >> >> PR target/71241 >> * testsuite/gcc.dg/torture/float128-nan.c: New test. >> >>

Re: [PATCH] Reject boolean/enum types in last arg of __builtin_*_overflow_p (take 2)

On Wed, Jun 15, 2016 at 08:08:22AM -0600, Martin Sebor wrote: > I like the idea of being able to use the built-ins for this, but > I think it would be confusing for them to follow subtly different > rules for C than for C++. Since the value of the last argument I think it isn't that hard to

[PATCH 2/3] Add support for arm*-*-phoenix* targets.

Is it ok for trunk? If possible, If possible, please merge it also to GCC-6 and GCC-5 branches. 2016-06-15 Jakub Sejdak * config.gcc: Add support for arm*-*-phoenix* targets. * config/arm/t-phoenix: New. * config/phoenix.h: New. --- gcc/ChangeLog

[PATCH 1/3] Disable libgcj and libgloss for Phoenix-RTOS targets.

This patch disables libgcj and libgloss in main configure.ac for new OS port - Phoenix-RTOS. Those libs are unnecessary to build GCC or newlib for arm-phoenix. Is it ok for trunk? If possible, If possible, please merge it also to GCC-6 and GCC-5 branches. 2016-06-15 Jakub Sejdak

[PATCH 3/3] Add support for arm*-*-phoenix* targets in libgcc.

Is it ok for trunk? If possible, If possible, please merge it also to GCC-6 and GCC-5 branches. 2016-06-15 Jakub Sejdak * config.host: Add suport for arm*-*-phoenix* targets. --- libgcc/ChangeLog | 4 libgcc/config.host | 7 +++ 2 files changed, 11

Re: [PATCH] Add port for Phoenix-RTOS on ARM platform.

Hello, > First of all, do you or your employer have a copyright assignment > to the FSF? The above link contains instructions on how to do that. > It is a necessary prerequisite to accepting any non-small change. Sorry for a late response, but it took me some time to fulfill requirements

Re: [PATCH] Reject boolean/enum types in last arg of __builtin_*_overflow_p (take 2)

On 06/15/2016 06:16 AM, Joseph Myers wrote: On Wed, 15 Jun 2016, Jakub Jelinek wrote: The only thing I'm unsure about is what to do with bitfield types. For __builtin_{add,sub,mul}_overflow it is not an issue, as one can't take address of a bitfield. For __builtin_{add,sub,mul}_overflow_p

Re: [PATCH] PR71275 ira.c bb_loop_depth

On 06/15/2016 04:03 PM, Alan Modra wrote: On Wed, Jun 15, 2016 at 11:49:50AM +0200, Bernd Schmidt wrote: On 06/15/2016 03:30 AM, Alan Modra wrote: Between these two calls to _gfortran_string_verify, if (verify(c4, "A", back = .true.) .ne. 3) call abort if (verify(c4, "AB") .ne. 0) call

Re: [PATCH] PR71275 ira.c bb_loop_depth

On Wed, Jun 15, 2016 at 11:49:50AM +0200, Bernd Schmidt wrote: > On 06/15/2016 03:30 AM, Alan Modra wrote: > >Between these two calls to _gfortran_string_verify, > > if (verify(c4, "A", back = .true.) .ne. 3) call abort > > if (verify(c4, "AB") .ne. 0) call abort > >it seems that gfortran is

Re: [PATCH][1/2] Move choose_mult_variant declaration and dependent declarations to expmed.h

On Wed, Jun 15, 2016 at 3:24 PM, Kyrill Tkachov wrote: > Hi all, > > This is a respin of > https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00951.html. > This just moves the necessary declarations to expmed.h so that a file that > includes > expmed.h can access the mult

Re: [5/7] Move the fix for PR65518

On Wed, Jun 15, 2016 at 10:52 AM, Richard Sandiford wrote: > This patch moves the fix for PR65518 to the code that checks whether > load-and-permute operations are supported. If the group size is > greater than the vectorisation factor, it would still be possible > to

Re: [4/7] Add a gather_scatter_info structure

On Wed, Jun 15, 2016 at 10:51 AM, Richard Sandiford wrote: > This patch just refactors the gather/scatter support so that all > information is in a single structure, rather than separate variables. > This reduces the number of arguments to a function added in patch 6. >

Re: [3/7] Fix load/store costs for strided groups

On Wed, Jun 15, 2016 at 10:50 AM, Richard Sandiford wrote: > vect_model_store_cost had: > > /* Costs of the stores. */ > if (STMT_VINFO_STRIDED_P (stmt_info) > && !STMT_VINFO_GROUPED_ACCESS (stmt_info)) > { > /* N scalar stores plus extracting the

[PATCH][1/2] Move choose_mult_variant declaration and dependent declarations to expmed.h

Hi all, This is a respin of https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00951.html. This just moves the necessary declarations to expmed.h so that a file that includes expmed.h can access the mult synthesis algorithms. Bootstrapped and tested on x86_64, aarch64, arm. Ok for trunk? Thanks,

[PATCH][vectorizer][2/2] Hook up mult synthesis logic into vectorisation of mult-by-constant

Hi all, This is a respin of https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00952.html following feedback. I've changed the code to cast the operand to an unsigned type before applying the multiplication algorithm and cast it back to the signed type at the end. Whether to perform the cast is now

Re: [2/7] Clean up vectorizer load/store costs

On Wed, Jun 15, 2016 at 10:49 AM, Richard Sandiford wrote: > Add a bit more commentary and try to make the structure more obvious. > The horrendous: > > if (grouped_access_p > && represents_group_p > && !store_lanes_p > && !STMT_VINFO_STRIDED_P

Re: [1/7] Remove unnecessary peeling for gaps check

On Wed, Jun 15, 2016 at 10:48 AM, Richard Sandiford wrote: > I recently relaxed the peeling-for-gaps conditions for LD3 but > kept them as-is for load-and-permute. I don't think the conditons > are needed for load-and-permute either though. No current load-and- >

Re: [PATCH] Add testcase for 4.8 aarch64 ICE

; 2016-06-15 Jakub Jelinek <ja...@redhat.com> > > * gcc.c-torture/compile/20160615-1.c: New test. > > --- gcc/testsuite/gcc.c-torture/compile/20160615-1.c.jj 2016-06-15 > 11:17:54.690689056 +0200 > +++ gcc/testsuite/gcc.c-torture/compile/20160615-1.c2016-06-15 &

Re: [PATCH] Backport PowerPC complex __float128 compiler support to GCC 6.x

On Wed, 15 Jun 2016, Michael Meissner wrote: > On Wed, Jun 15, 2016 at 11:01:05AM +0200, Richard Biener wrote: > > On Tue, 14 Jun 2016, Bill Schmidt wrote: > > > > > Hi Richard, > > > > > > As nobody else has replied, let me take a stab at this one. > > > > > > > On Jun 10, 2016, at 2:06 AM,

Re: [PATCH] Backport PowerPC complex __float128 compiler support to GCC 6.x

On Wed, Jun 15, 2016 at 11:01:05AM +0200, Richard Biener wrote: > On Tue, 14 Jun 2016, Bill Schmidt wrote: > > > Hi Richard, > > > > As nobody else has replied, let me take a stab at this one. > > > > > On Jun 10, 2016, at 2:06 AM, Richard Biener wrote: > > > > > > On Thu,

Re: [PATCH] PR71275 ira.c bb_loop_depth

On Wed, Jun 15, 2016 at 2:49 AM, Bernd Schmidt wrote: > On 06/15/2016 03:30 AM, Alan Modra wrote: >> >> Between these two calls to _gfortran_string_verify, >> if (verify(c4, "A", back = .true.) .ne. 3) call abort >> if (verify(c4, "AB") .ne. 0) call abort >> it seems that

Re: [PATCH] Reject boolean/enum types in last arg of __builtin_*_overflow_p (take 2)

On Wed, 15 Jun 2016, Jakub Jelinek wrote: > The only thing I'm unsure about is what to do with bitfield types. > For __builtin_{add,sub,mul}_overflow it is not an issue, as one can't take > address of a bitfield. For __builtin_{add,sub,mul}_overflow_p right now, > the C FE doesn't promote the

Re: [PATCH][AArch64] Enable -frename-registers at -O2 and higher

> On 10 Jun 2016, at 01:28, Jim Wilson wrote: > > On Tue, May 31, 2016 at 2:56 AM, James Greenhalgh > wrote: >> As you're proposing to have this on by default, I'd like to give a chance >> to hear whether there is consensus as to this being the

Re: [RFC][PATCH, vec-tails 00/10] Support vectorization of loop epilogues

On Thu, May 19, 2016 at 9:35 PM, Ilya Enkovich wrote: > Hi, > > This series is an extension of previous work on loop epilogue combining [1]. > > It introduces three ways to handle vectorized loop epilogues: combine it with > vectorized loop, vectorize it with masks,

Re: [PATCH, vec-tails 08/10] Support loop epilogue masking and low trip count loop vectorization

On Thu, May 19, 2016 at 9:46 PM, Ilya Enkovich wrote: > Hi, > > This patch enables vectorization of loop epilogues and low trip count > loops using masking. I wonder why we have the epilogue masking restriction with respect to the original vectorization factor - shouldn't

[PATCH] Add testcase for 4.8 aarch64 ICE

Hi! This testcase ICEs on aarch64 at -O2 on the 4.8 branch, got fixed with PR52714 fix (r208204). Is the testcase ok for trunk? Tested on x86_64-linux and i686-linux. 2016-06-15 Jakub Jelinek <ja...@redhat.com> * gcc.c-torture/compile/20160615-1.c: New test. --- gcc/testsuite

Re: [PATCH] Fix code emission for FAIL_ALLOC predictor

> Adding missing patch. > > Martin > >From 35ba97e0139d955c04e67ca157f8899bbb468bf1 Mon Sep 17 00:00:00 2001 > From: marxin > Date: Thu, 9 Jun 2016 17:51:38 +0200 > Subject: [PATCH] Fix code emission for FAIL_ALLOC predictor > > gcc/ChangeLog: > > 2016-06-13 Martin Liska

[C++ PATCH] Add testcase for 4.8 bug

Hi! The following testcase ICEs on the 4.8 branch, starting with r198314, but works in 4.9+. Is the testcase ok for trunk? Tested on x86_64-linux and i686-linux. 2016-06-15 Jakub Jelinek * g++.dg/cpp0x/ref-qual17.C: New test. ---

[PATCH] Reject boolean/enum types in last arg of __builtin_*_overflow_p (take 2)

On Tue, Jun 14, 2016 at 11:13:28AM -0600, Martin Sebor wrote: > >Here is an untested patch for that. Except that the middle-end considers > >conversions between BOOLEAN_TYPE and single bit unsigned type as useless, > >so in theory this can't work well, and in practice only if we are lucky >

Re: [PATCH, vec-tails 07/10] Support loop epilogue combining

On Thu, May 19, 2016 at 9:44 PM, Ilya Enkovich wrote: > Hi, > > This patch introduces support for loop epilogue combining. This includes > support in cost estimation and all required changes required to mask > vectorized loop. I wonder why you compute a minimum number of

Re: [PATCH] Fix code emission for FAIL_ALLOC predictor

Adding missing patch. Martin >From 35ba97e0139d955c04e67ca157f8899bbb468bf1 Mon Sep 17 00:00:00 2001 From: marxin Date: Thu, 9 Jun 2016 17:51:38 +0200 Subject: [PATCH] Fix code emission for FAIL_ALLOC predictor gcc/ChangeLog: 2016-06-13 Martin Liska *

Re: [PATCH, vec-tails 05/10] Check if loop can be masked

On Thu, May 19, 2016 at 9:42 PM, Ilya Enkovich wrote: > Hi, > > This patch introduces analysis to determine if loop can be masked > (compute LOOP_VINFO_CAN_BE_MASKED and LOOP_VINFO_REQUIRED_MASKS) > and compute how much masking costs. Maybe in a different patch, but it

Re: [PATCH, vec-tails 03/10] Support epilogues vectorization with no masking

On Thu, May 19, 2016 at 9:39 PM, Ilya Enkovich wrote: > Hi, > > This patch introduces changes required to run vectorizer on loop epilogue. > This also enables epilogue vectorization using a vector of smaller size. While the idea of epilogue vectorization sounds

Re: [PATCH] Optimize inserting value_type into std::vector

On 15/06/16 11:15 +0100, Jonathan Wakely wrote: * include/bits/stl_vector.h (vector::_S_insert_aux_assign): Define new overloaded functions. * include/bits/vector.tcc (vector::_M_insert_aux): Use new functions to avoid creating a redundant temporary. *

Re: RFA (gimplify): PATCH to implement C++ order of evaluation paper

On Tue, Jun 14, 2016 at 10:15 PM, Jason Merrill wrote: > As discussed in bug 71104, the C++ P0145 proposal specifies the evaluation > order of certain operations: > > 1. a.b > 2. a->b > 3. a->*b > 4. a(b1, b2, b3) > 5. b @= a > 6. a[b] > 7. a << b > 8. a >> b > > The second

Re: [patch, avr] Fix PR67353

On Mon, 2016-06-13 at 17:48 +0200, Georg-Johann Lay wrote: > Pitchumani Sivanupandi schrieb: > > > > $ avr-gcc test.c -Wno-misspelled-isr > > $ > What about -Werror=misspelled-isr? Updated patch. > > > > diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c > > index ba5cd91..587bdbc 100644

Re: [patch, avr] Fix PR67353

On Mon, 2016-06-13 at 17:48 +0200, Georg-Johann Lay wrote: > Pitchumani Sivanupandi schrieb: > > > > $ avr-gcc test.c -Wno-misspelled-isr > > $ > What about -Werror=misspelled-isr? Updated patch. > > > > diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c > > index ba5cd91..587bdbc 100644

[PATCH] Optimize inserting value_type into std::vector

* include/bits/stl_vector.h (vector::_S_insert_aux_assign): Define new overloaded functions. * include/bits/vector.tcc (vector::_M_insert_aux): Use new functions to avoid creating a redundant temporary. *

Re: [PATCH] PR71275 ira.c bb_loop_depth

On 06/15/2016 03:30 AM, Alan Modra wrote: Between these two calls to _gfortran_string_verify, if (verify(c4, "A", back = .true.) .ne. 3) call abort if (verify(c4, "AB") .ne. 0) call abort it seems that gfortran is assuming that parameters passed on the stack are unchanged. How? Is this

Re: [PATCH] PR 71439 - Only vectorize live PHIs that are inductions

On Wed, Jun 15, 2016 at 10:49 AM, Alan Hayward wrote: > For a PHI to be used outside the loop it needs to be vectorized. However > the > vectorizer currently will only vectorize PHIs that are an induction. > > This patch fixes PR 71439 by only allowing a live PHI to be

[Patch AArch64 2/2]Add missing vcond by rewriting it with vcond_mask/vec_cmp patterns.

Hi, This is the second patch. It rewrites vcond patterns using vcond_mask/vec_cmp patterns introduced in the first one. It also implements vcond patterns which were missing in the current AArch64 backend. After this patch, I have a simple follow up change enabling testing requirement

[Patch AArch64 1/2]Implement vcond_mask/vec_cmp patterns.

Hi, According to review comments, I split the original patch @ https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01182.html into two, as well as refined the comments. Here is the first one implementing vcond_mask/vec_cmp patterns on AArch64. These new patterns will be used in the second patch for

Re: [C++ Patch] One more error + error to error + inform and a subtler issue

Hi, On 15/06/2016 03:30, Jason Merrill wrote: On Tue, Jun 14, 2016 at 6:12 PM, Paolo Carlini wrote: constexpr-specialization.C:7:26: error: redeclaration ‘constexpr int foo(T) [with T = int]’ differs in ‘constexpr’ constexpr-specialization.C:6:16: error: from

[patch,avr] ad PR71103: also handle QImode SUBREGs of CONST

This patch handles the cases when subreg:QI of a CONST or LABEL_REF is to be moved to a QImode register. The original patch only handled SYMBOL_REFs. OK for trunk and backport? Johann -- gcc/ PR target/71103 * config/avr/avr.md (movqi): Handle loading subreg:qi (const).

Re: [PATCH] Backport PowerPC complex __float128 compiler support to GCC 6.x

On Tue, 14 Jun 2016, Bill Schmidt wrote: > Hi Richard, > > As nobody else has replied, let me take a stab at this one. > > > On Jun 10, 2016, at 2:06 AM, Richard Biener wrote: > > > > On Thu, 9 Jun 2016, Michael Meissner wrote: > > > >> I'm including the global reviewers

[7/7] Add negative and zero strides to vect_memory_access_type

This patch uses the vect_memory_access_type from patch 6 to represent the effect of a negative contiguous stride or a zero stride. The latter is valid only for loads. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Thanks, Richard gcc/ * tree-vectorizer.h

[6/7] Explicitly classify vector loads and stores

This is the main patch in the series. It adds a new enum and routines for classifying a vector load or store implementation. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Thanks, Richard gcc/ * tree-vectorizer.h (vect_memory_access_type): New enum.

[5/7] Move the fix for PR65518

This patch moves the fix for PR65518 to the code that checks whether load-and-permute operations are supported. If the group size is greater than the vectorisation factor, it would still be possible to fall back to elementwise loads (as for strided groups) rather than fail vectorisation

[4/7] Add a gather_scatter_info structure

This patch just refactors the gather/scatter support so that all information is in a single structure, rather than separate variables. This reduces the number of arguments to a function added in patch 6. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Thanks, Richard gcc/

[3/7] Fix load/store costs for strided groups

vect_model_store_cost had: /* Costs of the stores. */ if (STMT_VINFO_STRIDED_P (stmt_info) && !STMT_VINFO_GROUPED_ACCESS (stmt_info)) { /* N scalar stores plus extracting the elements. */ inside_cost += record_stmt_cost (body_cost_vec,

[2/7] Clean up vectorizer load/store costs

Add a bit more commentary and try to make the structure more obvious. The horrendous: if (grouped_access_p && represents_group_p && !store_lanes_p && !STMT_VINFO_STRIDED_P (stmt_info) && !slp_node) checks go away in patch 6. Tested on aarch64-linux-gnu and

[PATCH] PR 71439 - Only vectorize live PHIs that are inductions

For a PHI to be used outside the loop it needs to be vectorized. However the vectorizer currently will only vectorize PHIs that are an induction. This patch fixes PR 71439 by only allowing a live PHI to be vectorized if it is an induction. In addition, live PHIs need to pass a

[1/7] Remove unnecessary peeling for gaps check

I recently relaxed the peeling-for-gaps conditions for LD3 but kept them as-is for load-and-permute. I don't think the conditons are needed for load-and-permute either though. No current load-and- permute should load outside the group, so if there is no gap at the end, the final vector element

[0/7] Tweak vector load/store code

This patch series adds a new enum and routines for classifying a vector load or store implementation. Originally there were three motivations: (1) Reduce cut-&-paste (2) Make the chosen vectorisation strategy more obvious. At the moment this is derived implicitly from various other

Re: [PATCH] Fix SLP wrong-code with VECTOR_BOOLEAN_TYPE_P (PR tree-optimization/71259)

On 9 June 2016 at 14:46, Jakub Jelinek wrote: > On Thu, Jun 09, 2016 at 02:40:43PM +0200, Christophe Lyon wrote: >> > Bet it depends if this happens before the signal(SIGILL, sig_ill_handler); >> > call or after it. If before, then I guess you'd better rewrite the >> > long

Re: container method call shortcuts

On 14/06/16 22:04 +0200, François Dumont wrote: Hi Here is the patch to limit burden on compiler in finding out what is the right method to call eventually when we already know it. Very nice, OK for trunk, thanks.

Re: PR 71181 Avoid rehash after reserve

On 14/06/16 22:34 +0200, François Dumont wrote: On 14/06/2016 13:22, Jonathan Wakely wrote: On 13/06/16 21:49 +0200, François Dumont wrote: Hi I eventually would like to propose the attached patch. In tr1 I made sure we use a special past-the-end iterator that makes usage of lower_bound

RE: [PATCH] [ARC] New CPU C-define handler.

PING > -Original Message- > From: Claudiu Zissulescu > Sent: Thursday, May 19, 2016 1:58 PM > To: gcc-patches@gcc.gnu.org > Cc: Claudiu Zissulescu ; g...@amylaar.uk; > francois.bed...@synopsys.com > Subject: [PATCH] [ARC] New CPU C-define handler. > > This patch

RE: [PATCH] [ARC] Fix emitting jump tables for ARCv2

PING > -Original Message- > From: Claudiu Zissulescu > Sent: Tuesday, April 26, 2016 1:29 PM > To: gcc-patches@gcc.gnu.org > Cc: Claudiu Zissulescu ; g...@amylaar.uk; > francois.bed...@synopsys.com; jeremy.benn...@embecosm.com > Subject: [PATCH] [ARC] Fix emitting

RE: [PATCH 0/2] [ARC] Refurbish backend options

PING > -Original Message- > From: Claudiu Zissulescu > Sent: Monday, May 30, 2016 2:33 PM > To: gcc-patches@gcc.gnu.org > Cc: Claudiu Zissulescu ; g...@amylaar.uk; > francois.bed...@synopsys.com > Subject: [PATCH 0/2] [ARC] Refurbish backend options > > This series

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