> Provide versions of subreg_lowpart_offset and subreg_highpart_offset
> that work on mode sizes rather than modes. Also provide a routine
> that converts an lsb position to a subreg offset.
The position is in bits but all the other parameters and the return value are
in bytes so IMO this is a r
On Tue, 15 Nov 2016, Jakub Jelinek wrote:
> Hi!
>
> On Mon, Nov 14, 2016 at 10:58:51AM +0100, Jakub Jelinek wrote:
> > Working virtually out of Samoa.
> >
> > The following patch is an attempt to handle -fsanitize=undefined
> > for vectors. We already diagnose out of bounds accesses for vector
This should fix a performance regression caused by recent loop
distribution improvements. It trivially uses dependence analysis
(in addition to the existing alias oracle query) to determine
if we can use memcpy instead of memmove (no attempt is made yet to
cover the case where the dependence dis
Hi all,
This patch fixes the arm build failure due to out of range ubfx operands.
Combine now more aggressively generates zero_extracts
and it's up to the backend to reject invalid bit offsets and widths. And arm
seems to suffer from the same problems as aarch64 and s390
did in PR 77822.
My AR
I am testing the following to avoid undefined behavior when negating
a multiplication (basically extending a previous fix to properly handle
negative power of two).
Bootstrap / regtest running on x86_64-unknown-linux-gnu.
Richard.
2016-11-16 Richard Biener
PR middle-end/78305
Hi,
The below patch fixes c-c++-common/Wlogical-op-1.c for avr by
explicitly typedef'ing __INT32_TYPE for int and __INT16_TYPE__ for short
if the target's int size is less than 4 bytes.
The test assumes short is always smaller than int, and therefore does not
expect a warning when the
Since GCC 4.6 we aggressively prune bodies of GNU extern inline functions
which means that instrumenting them via -finstrument-functions doesn't
work because that takes the address of the function. Fixed by not
instrumenting those functions (we still instrument regular always-inline
functions and
On 09/11/16 16:19, Thomas Preudhomme wrote:
Hi,
This patch fixes the following ICE when building when compiling an empty FIQ
interrupt handler in ARM mode:
empty_fiq_handler.c:5:1: error: insn does not satisfy its constraints:
}
^
(insn/f 13 12 14 (set (reg/f:SI 13 sp)
(plus:SI (re
On Tue, 15 Nov 2016, Richard Biener wrote:
>
> Appearantly for some unknown reason we refuse to inline anything into
> functions calling cilk_spawn. That breaks fortified headers and
> all other always-inline function calls (intrinsics come to my mind as
> well).
>
> Bootstrapped and tested on
This patch adjusts the initialization of __sync built-in functions:
instead of conditionalizing on TARGET_LINUX_ABI, directly place the
target-hook #define in config/nios2/linux.h. This appears to be in line
with other similar ports, e.g. m68k.
Sebastian, this should solve your issue of not wanti
Eric Botcazou writes:
>> Provide versions of subreg_lowpart_offset and subreg_highpart_offset
>> that work on mode sizes rather than modes. Also provide a routine
>> that converts an lsb position to a subreg offset.
>
> The position is in bits but all the other parameters and the return
> value a
On Tue, 15 Nov 2016, Yuri Rumyantsev wrote:
> Hi All,
>
> Here is patch for non-masked epilogue vectoriziation.
>
> Bootstrap and regression testing did not show any new failures.
>
> Is it OK for trunk?
Ok for trunk.
I believe we ultimatively want to remove the new
--param and enable this by
On 15/11/16 19:25, Richard Earnshaw (lists) wrote:
On 15/11/16 16:48, Jiong Wang wrote:
On 15/11/16 16:18, Jakub Jelinek wrote:
I know nothing about the aarch64 return address signing, would all 3
or say
2 usually appear together without any separate pc advance, or are they
all
going to appear
The old code still built thanks to the brackets in the definition
of XVECEXP.
Tested on arc-elf and committed as obvious.
Thanks,
Richard
gcc/
* config/arc/arc.c (arc_loop_hazard): Add missing brackets.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 3bce7ef..98c7298 100
Needed this to test the effect of the SVE patches on other targets.
Tested on pdp11 and committed as obvious.
Thanks,
Richard
gcc/
* config/pdp11/pdp11.c: Include dbxout.h.
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 1dc3eef..8e2de14 100644
--- a/gcc/config/p
Segher Boessenkool writes:
> On Tue, Nov 15, 2016 at 12:33:06PM +, Richard Sandiford wrote:
>> The transformations made by make_compound_operation apply
>> only to scalar integer modes. The fix for PR70944 had enforced
>> that by returning early for vector modes at the top of the
>> function.
The ifconversion was failing because a move involving the lp_count was
not match by movsi_ne. This patch updates the constraints such that
movsi_ne will match. The failing test is dg-torture.exp=pr68955.c for
archs and without small data.
gcc/
2016-07-11 Claudiu Zissulescu
* config/a
> This isn't intended to change the behaviour, just rewrite the
> existing logic in a different (and hopefully clearer) way.
Yes, I agree that it's an improvement. A few remarks below.
> diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
> index ca6cced..7c0acf5 100644
> --- a/gcc/rtlanal.c
> +++ b/gcc/
gcc/
2016-07-21 Claudiu Zissulescu
* config/arc/arc.c (arc_ccfsm_post_advance): Handle return
instruction type.
---
gcc/config/arc/arc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 7eadb3c..a033dd0 1
gcc/
2016-06-30 Claudiu Zissulescu
* config/arc/arc-protos.h (insn_is_tls_gd_dispatch): Remove.
* config/arc/arc.c (arc_unspec_offset): New function.
(arc_finalize_pic): Change.
(arc_emit_call_tls_get_addr): Likewise.
(arc_legitimize_tls_address): Likewis
gcc/
2016-07-04 Claudiu Zissulescu
* config/arc/arc.md (mulsidi_600): Changed.
(umulsidi_600): Likewise.
(mul64): New pattern.
(mulu64): Likewise.
(mulsidi3): Changed.
(umulsidi3): Likewise.
---
gcc/config/arc/arc.md | 64
Hi,
This is a series of four pathes that are solving a number of dejagnu found
errors for ARC600 and ARCHS.
1st patch solves ARCHS issues when ifconverting movsi.ne instructions.
2nd patch cleans/refactors a bit our implementation.
3rd patch reimplements the mul64 support resolving all dejagnu r
> subreg_offset_from_lsb was supposed to be the inverse operation of
> subreg_lsb, which also returns a bit number.
It would have helped the reviewer to state it in the function comment. ;-)
> Should I change that to return a byte number as well?
Both functions are fine as-is, but mention that t
On Wed, Nov 16, 2016 at 10:16:16AM +, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > On Tue, Nov 15, 2016 at 12:33:06PM +, Richard Sandiford wrote:
> >> The transformations made by make_compound_operation apply
> >> only to scalar integer modes. The fix for PR70944 had enforced
Hi Thomas,
On 03/11/16 16:52, Thomas Preudhomme wrote:
Hi,
When using a callee-saved register to save the frame pointer the Thumb-1 prologue fails to save the callee-saved register before that. For ARM and Thumb-2 targets the frame pointer is handled as a special case but nothing is done for
T
Updated QuarkSE patch.
Ok to apply?
Claudiu
gcc/
2016-05-25 Claudiu Zissulescu
* config/arc/arc-arches.def: Add FPX quarkse instruction as valid
for arcem.
* config/arc/arc-c.def (__ARC_FPX_QUARK__): Define.
* config/arc/arc-cpus.def (quarkse_em): Add.
Maciej Rozycki writes:
> Fix `-mrelax-pic-calls' support for microMIPS code where the relocation
> produced is supposed to be R_MICROMIPS_JALR rather than R_MIPS_JALR.
> The lack of short delay support comes from a missed update to this code
> for microMIPS support and can be relieved as JALRS and
Maciej Rozycki writes:
> gcc/
> config/mips/mips.md (casesi_internal_mips16_): Add missing
>instruction prefixes throughout. Correct formatting.
>
> gcc/testsuite/
> * gcc.target/mips/code-readable-4.c (dg-final): Expect `dla'
> rather than `la'.
> ---
> OK
Maciej Rozycki writes:
> gcc/
> * config/mips/mips.md (casesi_internal_mips16_): Use the
> `ltu' rather than `leu' operation in the RTL pattern
> ---
> OK to apply?
Good spot. OK to commit.
Thanks,
Matthew
Maciej Rozycki writes:
> gcc/
> * config/mips/mips.md (casesi_internal_mips16_): Set
> `insn_count' to 11 rather than 16.
> ---
> OK to apply?
Good catch again. OK.
Thanks,
Matthew
Maciej Rozycki writes:
> gcc/
> * config/mips/mips.md (casesi_internal_mips16_):
> Explicitly switch between JR and JRC for the table jump. Adjust
> instruction count.
> ---
> OK to apply?
OK.
Thanks,
Matthew
When one uses ld.gold to build gcc, the thread sanitizer doesn't work,
because gold is more conservative when applying TLS relaxations than
ld.bfd. In this case a missing initial-exec attribute on a declaration
causes gcc to assume the general dynamic model. With ld.bfd this gets
relaxed to initial
On Wed, 16 Nov 2016, Richard Biener wrote:
I am testing the following to avoid undefined behavior when negating
a multiplication (basically extending a previous fix to properly handle
negative power of two).
Bootstrap / regtest running on x86_64-unknown-linux-gnu.
Richard.
2016-11-16 Richard
On Fri, Nov 11, 2016 at 06:32:43PM +0300, Maxim Ostapenko wrote:
> Tested on x86_64-unknown-linux-gnu. OK for mainline?
Ok (though the LOCAL_PATCHES file is missing in the patch).
> libsanitizer/ChangeLog:
>
> 2016-11-11 Maxim Ostapenko
>
> PR sanitizer/78307
> * ubsan/ubsan_hand
Thanks, Chung-Lin. This fixes the problem for RTEMS. The TLS support
works also.
On 16/11/16 10:53, Chung-Lin Tang wrote:
This patch adjusts the initialization of __sync built-in functions:
instead of conditionalizing on TARGET_LINUX_ABI, directly place the
target-hook #define in config/nios2/l
On Wed, Nov 16, 2016 at 11:56:07AM +0100, Markus Trippelsdorf wrote:
> When one uses ld.gold to build gcc, the thread sanitizer doesn't work,
> because gold is more conservative when applying TLS relaxations than
> ld.bfd. In this case a missing initial-exec attribute on a declaration
> causes gcc
On 16/11/16 14:00, Jakub Jelinek wrote:
On Fri, Nov 11, 2016 at 06:32:43PM +0300, Maxim Ostapenko wrote:
Tested on x86_64-unknown-linux-gnu. OK for mainline?
Ok (though the LOCAL_PATCHES file is missing in the patch).
Yes, I'm going to commit it in separate revision.
libsanitizer/ChangeLo
On Wed, 16 Nov 2016, Marc Glisse wrote:
> On Wed, 16 Nov 2016, Richard Biener wrote:
>
> > I am testing the following to avoid undefined behavior when negating
> > a multiplication (basically extending a previous fix to properly handle
> > negative power of two).
> >
> > Bootstrap / regtest runn
I'm pinging this as it breaks ASAN bootstrap.
On 11/11/2016 02:44 PM, Martin Liška wrote:
> Hello.
>
> Due to a stupid mistake I did, following patch is needed for the test-case
> to properly save previous gimplify_ctxp->live_switch_vars.
>
> Patch can bootstrap on ppc64le-redhat-linux and survi
On Fri, Nov 11, 2016 at 02:44:40PM +0100, Martin Liška wrote:
> Hello.
>
> Due to a stupid mistake I did, following patch is needed for the test-case
> to properly save previous gimplify_ctxp->live_switch_vars.
>
> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.
> I was
Approved and committed: Committed r24248
//Claudiu
> -Original Message-
> From: Andrew Burgess [mailto:andrew.burg...@embecosm.com]
> Sent: Saturday, April 30, 2016 12:17 AM
> To: Claudiu Zissulescu ; Joern Wolfgang
> Rennecke
> Cc: gcc-patches@gcc.gnu.org; noa...@mellanox.com
> Subject:
2016-11-12 21:21 GMT+01:00 Janus Weil :
Index: gcc/fortran/class.c
===
--- gcc/fortran/class.c(Revision 242066)
+++ gcc/fortran/class.c(Arbeitskopie)
@@ -2970,7 +2970,6 @@ gfc_get_tbp_symtree (gfc_symtr
On Mon, 14 Nov 2016, Matthew Fortune wrote:
> > This however requires the correct annotation of branch targets as code,
> > because the ISA mode is not relevant for data symbols and is therefore
> > not recorded for them.
>
> I wonder if it would have been possible to add the ISA mode to data
>
On 11/16/2016 12:35 PM, Jakub Jelinek wrote:
> On Fri, Nov 11, 2016 at 02:44:40PM +0100, Martin Liška wrote:
>> Hello.
>>
>> Due to a stupid mistake I did, following patch is needed for the test-case
>> to properly save previous gimplify_ctxp->live_switch_vars.
>>
>> Patch can bootstrap on ppc64le-
On Wed, Nov 16, 2016 at 08:45:35AM +, Kyrill Tkachov wrote:
> This patch fixes the arm build failure due to out of range ubfx operands.
> Combine now more aggressively generates zero_extracts
> and it's up to the backend to reject invalid bit offsets and widths. And arm
> seems to suffer from
Hi Dominik,
On 16/11/16 12:16, Dominik Vogt wrote:
On Wed, Nov 16, 2016 at 08:45:35AM +, Kyrill Tkachov wrote:
This patch fixes the arm build failure due to out of range ubfx operands.
Combine now more aggressively generates zero_extracts
and it's up to the backend to reject invalid bit of
Hello
Following patch is a candidate that re-writes VAR_DECLs that are
is_gimple_reg_type with:
my_char_25 = ASAN_POISON ();
that is eventually transformed to:
__builtin___asan_report_use_after_scope_noabort ("my_char", 1);
at places where my_char_25 is used. That introduces a new entry point
to
Eric Botcazou writes:
>> This isn't intended to change the behaviour, just rewrite the
>> existing logic in a different (and hopefully clearer) way.
>
> Yes, I agree that it's an improvement. A few remarks below.
>
>> diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
>> index ca6cced..7c0acf5 100644
>>
On 11/16/2016 01:25 PM, Martin Liška wrote:
> Hello
>
> Following patch is a candidate that re-writes VAR_DECLs that are
> is_gimple_reg_type with:
> my_char_25 = ASAN_POISON ();
>
> that is eventually transformed to:
> __builtin___asan_report_use_after_scope_noabort ("my_char", 1);
>
> at place
On 11/15/2016 05:46 PM, Jan Hubicka wrote:
> Yep, zero is definitly valid hash value:0
>
> Patch is OK. We may consider backporting it to release branches.
> Honza
Thanks, sending v2 as I found an error in the previous version.
Changes from last version:
- comments for ctors are just in header fi
On Tue, Nov 15, 2016 at 4:54 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Tue, Nov 15, 2016 at 1:44 PM, Richard Sandiford
>> wrote:
>>> We previously stored the number of loop iterations rather
>>> than the number of latch iterations.
>>
>> So ->nb_iterations was unused without SV
On Wed, Nov 16, 2016 at 01:25:04PM +0100, Martin Liška wrote:
>
> +
> +/* Expand the ASAN_{LOAD,STORE} builtins. */
Stale comment.
> +
> +bool
> +asan_expand_poison_ifn (gimple_stmt_iterator *iter,
> + bool *need_commit_edge_insert)
> +{
...
> + use_operand_p use_p;
> + i
On Tue, Nov 15, 2016 at 09:11:56PM +, Andrew Stubbs wrote:
> On 15/11/16 21:06, Michael Meissner wrote:
> >Now, that I have a little time, I can look into this, to at least make
> >predicate and peepholes match. There is some other stuff (support for the
> >new
> >load/store that were added t
On 11/15/2016 11:55 PM, Alan Modra wrote:
This is a fix for my PR70890 patch, which incorrectly removed all
REG_EQUIV notes rather than just one regarding a reg that dies.
Bootstrapped and regression tested powerpc64le-linux,
x86_64-linux, and mips-linux. OK to apply?
PR rtl-optimizatio
On Tue, Nov 15, 2016 at 10:07 PM, David Malcolm wrote:
> On Mon, 2016-11-14 at 16:14 +0100, Richard Biener wrote:
>> On Fri, Nov 11, 2016 at 10:15 PM, David Malcolm
>> wrote:
>> > Changed in this version:
>> >
>> > * Rather than running just one pass, run *all* passes, but start at
>> > the giv
On Tue, Nov 15, 2016 at 11:33 AM, Segher Boessenkool
wrote:
> So far all target implementations of the separate shrink-wrapping hooks
> use the DF LIVE info to figure out around which basic blocks the non-
> volatile registers need to be saved. This is done by looking at the
> IN+GEN+KILL sets of
On Thu, Nov 10, 2016 at 9:52 PM, Dominik Vogt wrote:
> On Wed, Nov 09, 2016 at 03:46:38PM +0100, Richard Biener wrote:
>> On Wed, Nov 9, 2016 at 3:30 PM, Dominik Vogt wrote:
>> > Something like the attached patch? Robin and me have spent quite
>> > some time to figure out the new pattern. Two q
Hi Janus,
thanks for the quick review. Committed as r242490.
Regards,
Andre
On Tue, 15 Nov 2016 22:24:43 +0100
Janus Weil wrote:
> Hi Andre,
>
> > attached patch fixes the issue raised. The issue here was, that a copy of
> > the base class was generated and its address passed to the
>
Maciej Rozycki writes:
> On Mon, 14 Nov 2016, Matthew Fortune wrote:
>
> > > This however requires the correct annotation of branch targets as
> > > code, because the ISA mode is not relevant for data symbols and is
> > > therefore not recorded for them.
> >
> > I wonder if it would have been pos
On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
> The two operations DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_deref
> were
> designed as shortcut operations when LR is signed with A key and using
> function's CFA as salt. This is the default behaviour of return address
> signing so
On Wed, Nov 16, 2016 at 02:54:56PM +0100, Mark Wielaard wrote:
> On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
> > The two operations DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_deref
> > were
> > designed as shortcut operations when LR is signed with A key and using
> > function's CF
The options -mfpu=neon and -mfpu=vfp have always meant a specific
version of neon and vfp, but common usage seems to misunderstand this.
To help clarify things I've added a couple of new option values to the
-mfpu= option and have now documented the existing names as aliases.
As discussed at the
On Wed, 16 Nov 2016, Richard Biener wrote:
On Wed, 16 Nov 2016, Marc Glisse wrote:
On Wed, 16 Nov 2016, Richard Biener wrote:
I am testing the following to avoid undefined behavior when negating
a multiplication (basically extending a previous fix to properly handle
negative power of two).
On 11/11/16 15:42, James Greenhalgh wrote:
Hi,
Finally, having added support for single-step DFmode to HFmode conversions,
this patch adds support for _Float16 to the ARM back-end.
That means making sure that only __fp16 promotes and adding similar hooks to
those used in the AArch64 port givin
On Wed, 16 Nov 2016, Marc Glisse wrote:
> On Wed, 16 Nov 2016, Richard Biener wrote:
>
> > On Wed, 16 Nov 2016, Marc Glisse wrote:
> >
> > > On Wed, 16 Nov 2016, Richard Biener wrote:
> > >
> > > > I am testing the following to avoid undefined behavior when negating
> > > > a multiplication (ba
On Mon, Nov 14, 2016 at 5:40 AM, Michael Matz wrote:
> Hi,
>
> I'm working on this since some time; I have various extensions to it in
> the works (hinted at in the comments), but haven't yet stabilized them.
> But this is useful on its own as is, so lets get it out before midnight at
> UTC-12 (he
On Nov 07 2016, Mike Stump wrote:
> On Nov 1, 2016, at 8:46 AM, Tamar Christina wrote:
>>
>> A glibc update recently broke this test by adding a CPP
>> macro that uses the ## string function which traditional-cpp
>> does not support.
>> The change in glibc that made the test fail is from
>> 696
On 11/11/16 15:42, James Greenhalgh wrote:
Hi,
Conversions from double precision floats to the ARM __fp16 are required
to round only once.
This patch adds a functions named __gnu_d2h_ieee and
__gnu_d2h_alternative for double to __fp16 conversions in IEEE and ARM
alternative format. The make us
This patch to the Go frontend separates comparable and incomparable
types. Otherwise we can create an incomparable type for, say, a map
bucket, and have that mislead us into creating an incomparable user
type. If the user type is then used in a map, the program crashes.
This fixes the gccgo vers
> Well, I think it's probably grammatical, but how about:
>
> If the register representation of a non-scalar mode has holes in it,
> we expect the scalar units to be concatenated together, with the holes
> distributed evenly among the scalar units. Each scalar unit must occupy
> at least
On Tue, Nov 15, 2016 at 9:03 PM, Bill Schmidt
wrote:
> Hi,
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77848 identifies a situation
> where if-conversion causes degradation when the if-converted loop is not
> subsequently vectorized. The if-conversion pass does not have a cost
> model to avo
On Nov 14 2016, Michael Matz wrote:
> PR missed-optimization/77881
> * combine.c (simplify_comparison): Remove useless subregs
> also inside the loop, not just after it.
> (make_compound_operation): Recognize some subregs as being
> masking as well.
This breaks gcc.
This patch backports the following patches that Chung-Lin committed to
trunk back in May to gomp4:
https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01146.html
https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01147.html
https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01148.html
https://gcc.gnu.org/
Hi,
The patch primarily fixes an ICE with out-of-range values to
the __builtin_msa_insve* intrinsics.
The compiler segfaults in mips_legitimize_const_move () as it tries
to split symbol that has NULL_RTX value and gets here because the patterns
reject the operand and a new move for the constant
On Wed, 16 Nov 2016, Matthew Fortune wrote:
> > Based on this observation however I have determined that moving
> > multilib
> > and related flags such as `-mabi=n64' and possibly also `-Wl,-rpath,...'
> > from `$board_info(...,cflags)' over to `$board_info(...,multilib_flags)'
> > helps a bit an
Found some time to look into this again.
> Index: tree-ssa-propagate.c
> ===
> --- tree-ssa-propagate.c(revision 240133)
> +++ tree-ssa-propagate.c(working copy)
> @@ -1105,10 +1105,10 @@ substitute_and_fold_dom_walker
>
> This is causing all test names to depend on $srcdir. A test name should never
> include the value of $srcdir.
Sorry about that, committed a fix as r242500 under the obvious rule.
Thanks,
Tamar
>
> Andreas.
>
> --
> Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196
> BA
On Wed, 16 Nov 2016, Richard Biener wrote:
On Wed, 16 Nov 2016, Marc Glisse wrote:
On Wed, 16 Nov 2016, Richard Biener wrote:
On Wed, 16 Nov 2016, Marc Glisse wrote:
On Wed, 16 Nov 2016, Richard Biener wrote:
I am testing the following to avoid undefined behavior when negating
a multipli
Forgot to include the committed patch.
> -Original Message-
> From: Tamar Christina
> Sent: 16 November 2016 15:55
> To: Andreas Schwab; Mike Stump
> Cc: GCC Patches; r...@cebitec.uni-bielefeld.de; nd
> Subject: RE: [PATCH][GCC/TESTSUITE] Make test for traditional-cpp depend
> on
>
> >
>
I'm still looking for a review of the patch below, first posted
on 10/28 and last updated/pinged last Wednesday:
https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00896.html
Thanks
On 11/09/2016 03:49 PM, Martin Sebor wrote:
The attached minor update to the patch also resolves bug 77784 that
poi
* Claudiu Zissulescu [2016-05-30 14:32:38
+0200]:
> Update the ARC specific tests.
>
> OK to apply?
> Claudiu
>
> gcc/
> 2016-05-26 Claudiu Zissulescu
>
> * testsuite/gcc.target/arc/abitest.S: New file.
> * testsuite/gcc.target/arc/va_args-1.c: Likewise.
> * testsuite/gcc
On 11/11/16 15:42, James Greenhalgh wrote:
Hi,
This patch adds the half-to-double conversions, both as library functions,
or when supported in hardware, using the appropriate instructions.
That means adding support for the __gnu_d2h_{ieee/alternative} library calls
added in patch 2/4, and prov
On 11/16/2016 02:07 PM, Jakub Jelinek wrote:
> On Wed, Nov 16, 2016 at 01:25:04PM +0100, Martin Liška wrote:
>>
>> +
>> +/* Expand the ASAN_{LOAD,STORE} builtins. */
>
> Stale comment.
Fixed.
>
>> +
>> +bool
>> +asan_expand_poison_ifn (gimple_stmt_iterator *iter,
>> +bool
Hi,
On Wed, 16 Nov 2016, Marc Glisse wrote:
> > > The first sentence about ORing the sign bit sounds strange (except for a
> > > sign-magnitude representation). With 2's complement, INT_MIN is -2^31, the
> > > divisors are the 2^k and -(2^k). -2 * 2^30 yields INT_MIN, but your test
> > > misses -
As the patch quite significantly slowed down tramp3d, there's analysis
of # of variables which are poisoned by the sanitizer:
== normal variables ==
24 B: 348x (5.80%)
16 B: 273x (4.55%)
8 B: 237x (3.95%)
1 B: 177x (2.95%)
4 B: 119x (1.98%)
40 B: 89x (1.48%)
144 B:
Hi,
On Wed, 16 Nov 2016, Michael Matz wrote:
> > Looks good to me, thanks.
>
> An integer X is a power of two if and only if
> X & -X == 0 (&& X != 0 if you want to exclude zero)
Nonsense. It's X & -X == X (or X & (X-1) == 0) of course, and doesn't
handle negative numbers. Still, no popco
On 16/11/16 13:10, Michael Meissner wrote:
Yeah, SFmode and DFmode should not have the TARGET_{S,D}F_FPR checks.
So, I can safely resolve my initial problem by simply removing them? And
that wouldn't break the other use of that predicate?
But a secondary problem is the early clobber in the
On 11/15/2016 05:31 PM, Andrew Senkevich wrote:
2016-11-15 17:56 GMT+03:00 Jeff Law :
On 11/15/2016 05:55 AM, Andrew Senkevich wrote:
2016-11-11 14:16 GMT+03:00 Uros Bizjak :
--- a/gcc/genmodes.c
+++ b/gcc/genmodes.c
--- a/gcc/init-regs.c
+++ b/gcc/init-regs.c
--- a/gcc/machmode.h
+++ b/gcc/
On Wed, 16 Nov 2016, Michael Matz wrote:
Hi,
On Wed, 16 Nov 2016, Marc Glisse wrote:
The first sentence about ORing the sign bit sounds strange (except for a
sign-magnitude representation). With 2's complement, INT_MIN is -2^31, the
divisors are the 2^k and -(2^k). -2 * 2^30 yields INT_MIN, b
On Wed, Nov 16, 2016 at 05:01:31PM +0100, Martin Liška wrote:
> + use_operand_p use_p;
> + imm_use_iterator imm_iter;
> + FOR_EACH_IMM_USE_FAST (use_p, imm_iter, poisoned_var)
> +{
> + gimple *use = USE_STMT (use_p);
> + if (is_gimple_debug (use))
> + continue;
> +
> + bui
Later patches will make machmode.h rely on wide-int.h and the
new poly-int.h, so it needs to appear later in the coretypes.h
include list.
Previously machmode.h included insn-modes.h, which as well as
the main mode enum contains configuration information like
MAX_BITSIZE_MODE_ANY_INT. This still
Hi James,
On 11/11/16 15:42, James Greenhalgh wrote:
Hi,
I'm adapting this patch from work started by Matthew Wahab.
Conversions from double precision floats to the ARM __fp16 are required
to round only once. A conversion function for double to __fp16 to
support this on soft-fp targets. This a
Thanks, Richard! I'll follow up with these changes over the next day or
two. Appreciate all the help!
Bill
On Wed, 2016-11-16 at 16:08 +0100, Richard Biener wrote:
> On Tue, Nov 15, 2016 at 9:03 PM, Bill Schmidt
> wrote:
> > Hi,
> >
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77848 identi
This may no longer be necessary with the current version
of the SVE patches, but it does at least make things consistent
with the TYPE_MODE/SET_TYPE_MODE split.
Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
Thanks,
Richard
[ This patch is part of the SVE series posted here:
I'm looking for an approval of the attached patch.
I've adjusted the documentation based on Sandra's input (i.e.,
documented the negative of the option rather than the positive;
thank you for the review, btw.)
On 11/08/2016 08:13 PM, Martin Sebor wrote:
The -fprintf-return-value optimization ha
This change makes the code less sensitive to the exact type of the mode,
i.e. it forces a conversion where necessary. This becomes important
when wrappers like scalar_int_mode and scalar_mode can also be used
instead of machine_mode.
Using rtx_mode_t also abstracts away the representation. The f
ieee_support_halting only checked the availability of status
flags, not trapping support. On some targets the later can
only be checked at runtime: feenableexcept reports if
enabling traps failed.
So check trapping support by enabling/disabling it.
Updated the test that enabled trapping to check
Hi all,
As the PR says we have an RTL checking failure that occurs when building libgcc
for aarch64.
The expander code for addsi3 takes the REGNO of a SUBREG in operands[1]. The
three operands
in the failing case are:
{(reg:SI 78), (subreg:SI (reg:DI 77) 0), (subreg:SI (reg:DI 73 [ ivtmp.9 ]) 0
On 11/16/2016 05:52 PM, Richard Sandiford wrote:
Using rtx_mode_t also abstracts away the representation. The fact that
it's a std::pair rather than a custom class isn't important to users of
the interface.
Looks borderline obvious to me. OK.
Bernd
On Wed, Nov 16, 2016 at 04:15:10PM +, Andrew Stubbs wrote:
> On 16/11/16 13:10, Michael Meissner wrote:
> >Yeah, SFmode and DFmode should not have the TARGET_{S,D}F_FPR checks.
>
> So, I can safely resolve my initial problem by simply removing them?
> And that wouldn't break the other use of t
1 - 100 of 179 matches
Mail list logo
