Re: [PATCH, rs6000] GIMPLE folding for vector compares

Hi Will, On Thu, Oct 12, 2017 at 03:03:12PM -0500, Will Schmidt wrote: > * config/rs6000/rs6000.c: (rs6000_gimple_fold_builtin) Add support for > folding of vector compares. (builtin_function_type) Add compare > builtins to the list of functions having unsigned arguments. >

[PATCH] Add gnu::unique_ptr

From: Trevor Saunders I had a go at updating Trevor's unique_ptr patch from July ( https://gcc.gnu.org/ml/gcc-patches/2017-07/msg02084.html ) One of the sticking points was what to call the namespace; there was wariness about using "gtl" as the name. Richi proposed

Re: [PATCH, rs6000] Correct unaligned_load vector cost for Power9

On Mon, Oct 09, 2017 at 03:46:17PM -0500, Pat Haugen wrote: > Power9 has efficient unaligned load insns. The following patch fixes the > cost to reflect that. There was no similar code for the unaligned_store > case. Bootstrap/regtest on powerpc64le-linux with no new regressions. > Ok for trunk?

Re: [PATCH 09/22] Enable building libbacktrace with Intel CET

"Tsimbalist, Igor V" writes: > Enable building libbacktrace with CET options. > > libbacktrace/ > * configure.ac: Add CET_FLAGS to EXTRA_FLAGS. > * aclocal.m4: Regenerate. > * Makefile.in: Likewise. > * configure: Likewise. > +if test

Re: [PATCH 08/22] Add Intel CET support for EH in libgcc.

On Thu, 12 Oct 2017, Tsimbalist, Igor V wrote: > * unwind.inc (_Unwind_RaiseException_Phase2): Use FRAMES_P_DECL, > FRAMES_VAR_DECL_1, FRAMES_VAR_INC and FRAMES_P_UPDATE. > (_Unwind_RaiseException): Use FRAMES_VAR_DECL, FRAMES_VAR_P and > FRAMES_VAR. >

RE: [PATCH 07/22] Enable building libgcc with CET options.

> -Original Message- > From: Joseph Myers [mailto:jos...@codesourcery.com] > Sent: Thursday, October 12, 2017 10:36 PM > To: Tsimbalist, Igor V > Cc: gcc-patches@gcc.gnu.org; Jeff Law ; i...@airs.com > Subject: Re: [PATCH 07/22] Enable

Re: Make more use of byte_lowpart_offset

On 08/23/2017 04:53 AM, Richard Sandiford wrote: > This patch uses byte_lowpart_offset in places that open-coded the > calculation. > > Tested on aarch64-linux-gnu and x86_64-linux-gnu, and by making sure > that there were no differences in testsuite assembly output for one > target per CPU. OK

Re: [PATCH] Fix bitmap_bit_in_range_p (PR tree-optimization/82493).

On 10/11/2017 12:13 AM, Martin Liška wrote: > 2017-10-10 Martin Liska > > PR tree-optimization/82493 > * sbitmap.c (bitmap_bit_in_range_p): Fix the implementation. > (test_range_functions): New function. > (sbitmap_c_tests): Likewise. > *

Re: [PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

On Fri, 2017-09-22 at 14:11 -0700, Andrew Pinski wrote: > On Fri, Sep 22, 2017 at 11:39 AM, Jim Wilson > wrote: > > > > On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski > > wrote: > > > > > > Two overall comments: > > > * What about splitting

[PATCH 21/22] Enable building libitm with Intel CET

Enable building libitm with Intel CET options. libitm/ * Makefile.in: Regenerate. * acinclude.m4: Add enable.m4 and cet.m4. * config/x86/sjlj.S (_ITM_beginTransaction): Save Shadow Stack pointer. (GTM_longjmp): Restore Shadow Stack pointer. *

[PATCH 20/22] Enable building libobjc with Intel CET

Enable building libobjc with Intel CET options. libobjc/ * Makefile.in: Regenerate. * aclocal.m4: Likeiwse. * configure: Likewise. * configure.ac: Set CET_FLAGS. Update XCFLAGS. 0020-Enable-building-libobjc-with-Intel-CET.PATCH Description:

[PATCH 19/22] Enable building libgfortran with Intel CET

Enable building libgfortran with Intel CET options. libgfortran/ * acinclude.m4: Add enable.m4, cet.m4. * configure: Regenerate. * configure.ac: Set CET_FLAGS. Update AM_FCFLAGS, AM_CFLAGS, CFLAGS. 0019-Enable-building-libgfortran-with-Intel-CET.PATCH

Re: [PATCH] C++: show location of unclosed extern "C" specifications (v2)

On Thu, Oct 12, 2017 at 2:45 PM, David Malcolm wrote: > - put the note on the string-literal, rather than the extern: > note: 'extern "C"' linkage started here > extern "C" { > ^~~ Maybe a range spanning both tokens? OK with or without that change.

[patch] Fix PR debug/82509

Hi, this PR reports a couple of problems with the support of the DW_AT_endianity attribute associated with the scalar_storage_order source attribute: it does not persist through typedefs and it can contaminate native order DIEs. The attached patch revamps it by associating native order DIEs

[PATCH 18/22] Enable building libmpx with Intel CET

Enable building libmpx with Intel CET options. libmpx/ * Makefile.in: Regenerate. * acinclude.m4: Add enable.m4 and cet.m4. * configure: Regenerate. * configure.ac: Set CET_FLAGS. Update XCFLAGS. * mpxrt/Makefile.am: Update libmpx_la_CFLAGS. *

Re: [PATCH 07/22] Enable building libgcc with CET options.

On Thu, 12 Oct 2017, Tsimbalist, Igor V wrote: > Enable building libgcc with CET options by default on Linux/x86 if > binutils supports CET v2.0. > It can be disabled with --disable-cet. It is an error to configure > GCC with --enable-cet if bintuiils doesn't support CET v2.0. > > config/ >

[PATCH 17/22] Enable building libquadmath with Intel CET

Enable building libquadmath with Intel CET options. libquadmath/ * Makefile.am: Update AM_CFLAGS. * Makefile.in: Regenerate: * acinclude.m4: Add enable.m4 and cet.m4. * configure: Regenerate. * configure.ac: Set CET_FLAGS. Update XCFLAGS.

[PATCH 16/22] Enable building libssp with Intel CET

Enable building libssp with Intel CET options. libssp/ * Makefile.am: Update AM_CFLAGS. * Makefile.in: Regenerate. * configure: Likewise. * aclocal.m4: Likewise. * configure.ac: Set CET_FLAGS. Update XCFLAGS.

[PATCH 15/22] Enable building libvtv with Intel CET

Enable building libvtv with Intel CET options. libvtv/ * acinclude.m4: Add enable.m4 and cet.m4. * libvtv/configure: Regenerate. * libvtv/configure.ac: Set CET_FLAGS. Update XCFLAGS. 0015-Enable-building-libvtv-with-Intel-CET.PATCH Description:

[PATCH 14/22] Enable building libsanitizer with Intel CET

Enable building libsanitizer with Intel CET options. libsanitizer/ * acinclude.m4: Add enable.m4 and cet.m4. * Makefile.in: Regenerate. * asan/Makefile.am: Update AM_CXXFLAGS. * asan/Makefile.in: Regenerate. * configure: Likewise. * configure.ac:

[PATCH 13/22] Enable building libstdc++-v3 with Intel CET

Enable building libstdc++v3 with CET options. libstdc++-v3/ * acinclude.m4: Add cet.m4. * configure.ac: Set CET_FLAGS. Update EXTRA_CFLAGS. * libsupc++/Makefile.am: Add EXTRA_CFLAGS. * Makefile.in: Regenerate. * configure: Likewise. *

[PATCH 12/22] Enable building libgomp with Intel CET

Enable building libgomp with CET options. libgomp/ * configure.ac: Set CET_FLAGS, update XCFLAGS and FCFLAGS. * acinclude.m4: Add cet.m4. * configure: Regenerate. * Makefile.in: Likewise. * testsuite/Makefile.in: Likewise

[PATCH 11/22] Enable building libatomic with Intel CET

Enable building libatomic with CET options. libatomic/ * configure.ac: Set CET_FLAGS, update XCFLAGS. * acinclude.m4: Add cet.m4 and enable.m4. * configure: Regenerate. * Makefile.in: Likewise. * testsuite/Makefile.in: Likewise.

[PATCH 10/22] Enable building libcilkrts with Intel CET

Enable building libcilkrts with CET options. libcilkrts/ * Makefile.am: Add AM_CXXFLAGS and XCXXFLAGS. * configure.ac: Set CET_FLAGS, update XCFLAGS, XCXXFLAGS. * Makefile.in: Regenerate. * aclocal.m4: Likewise. * configure: Likewise.

[PATCH, rs6000] GIMPLE folding for vector compares

Hi, Add support for gimple folding of vec_cmp_{eq,ge,gt,le,ne} for the integer data types. This adds a handful of entries to the switch statement in builtin_function_type for those builtins having unsigned arguments. Three entries are added to vsx.md to enable vcmpne[bhw]

[PATCH] (gimple) Allow integer return type from vector compares

Hi, Update the logic in verify_gimple_comparision to allow a vector integer result from a vector comparison, where it previously was limited to only allowing compares with boolean results. This allows powerpc intrinsics such as this one to build (after gimple folding): vector bool int

[PATCH 09/22] Enable building libbacktrace with Intel CET

Enable building libbacktrace with CET options. libbacktrace/ * configure.ac: Add CET_FLAGS to EXTRA_FLAGS. * aclocal.m4: Regenerate. * Makefile.in: Likewise. * configure: Likewise. Igor 0009-Enable-building-libbacktrace-with-Intel-CET.PATCH Description:

[PATCH 08/22] Add Intel CET support for EH in libgcc.

Control-flow Enforcement Technology (CET), published by Intel, Introduces the Shadow Stack feature, which ensures a return from a function is done to exactly the same location from where the function was called. When EH is present the control-flow transfer may skip some stack frames and the shadow

[PATCH 07/22] Enable building libgcc with CET options.

Enable building libgcc with CET options by default on Linux/x86 if binutils supports CET v2.0. It can be disabled with --disable-cet. It is an error to configure GCC with --enable-cet if bintuiils doesn't support CET v2.0. config/ * cet.m4: New file gcc/ * config.gcc

[PATCH] Fix various arithmetic patterns with %[abcd]h destination (PR target/82524)

Hi! As mentioned in the PR, there are two bugs in these. One is that the zero_extract destination is effectively another input operand (for the remaining bits that are unchanged) and thus the constraint can't be =Q, but has to be +Q. And the other problem is that then LRA ICEs whenever it has 3

[PATCH] Improve rotate fold-const pattern matching (PR target/82498)

Hi! Marc in the PR mentioned that it is not really good that the recommended rotate pattern is recognized only during forwprop1 and later, which is after einline and that inlining or early opts could have changed stuff too much so that we wouldn't recogize it anymore. The following patch handles

[PATCH] Avoid UB in ia32intrin.h rotate patterns (PR target/82498)

Hi! The ia32intrin.h rotate intrinsics require the second argument to be in between 1 and 31 (or 63), otherwise they invoke UB. But, we can do much better while generating the same instruction when optimizing, so the following patch uses the patterns we pattern recognize well and where the

Re: [patch, fortran] New take on PR 82373

On Thu, Oct 12, 2017 at 08:21:46PM +0200, Thomas Koenig wrote: > > after some thought, I think the PR can be fixed by something > far less invasive than my previous patch. > > The new version of the patch simply issues an error for a > non-printable character (which should never be legal). >

Re: [PATCH] Improve x86 and + rotate (PR target/82498)

On Thu, Oct 12, 2017 at 10:40:22AM +0200, Uros Bizjak wrote: > > So, if you aren't against it, I can extend the patch to handle the 4 > > other mask patterns; as for other modes, SImode is what is being handled > > already, DImode is not a problem, because the FEs truncate the shift counts > > to

Go patch committed: Fix import of indirectly imported type alias

When the Go frontend imported a reference to an indirectly imported type aliases, it was looking for the " = " before the optional package name that appears for an indirect reference, but the exporter was putting it after. This patch fixes that. The test case is https://golang.org/cl/70290, and

[C++ PATCH] cp_expr tweak and delete unused enumerations

The cp_expr class doesn't have a const-qualified operator * accessor. This leaves one with a confusing error message if one ever tries to dereference a constant cp_expr object: const cp_expr thing = ...; tree bob = *thing; // ERROR What happens is the non-const operator * is not suitable,

RE: 0006-Part-6.-Add-x86-tests-for-Intel-CET-implementation

Attached is an updated patch according to your comments. New tests are added to test ICF optimization in presence of nocf_check attribute. Igor > -Original Message- > From: Tsimbalist, Igor V > Sent: Tuesday, September 19, 2017 11:30 PM > To: Uros Bizjak > Cc:

Increase base of profile probabilities

Hi, this patch makes profile probability use more precise representation and takes care of places where 32bit artithmetic will possibly overflow. This will make it possible to drop counts on edges next. Bootstrapped/regtested x86_64-linux, comitted. Honza * profile-count.c

RE: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET

Uros, Attached is an updated patch. The main difference is in option name and attribute name change. Other code is the same. Igor > -Original Message- > From: Tsimbalist, Igor V > Sent: Tuesday, September 19, 2017 5:06 PM > To: Uros Bizjak ; gcc-patches@gcc.gnu.org

[PATCH] C++: show location of unclosed extern "C" specifications (v2)

On Wed, 2017-10-11 at 15:51 -0400, Jason Merrill wrote: > On Tue, Sep 26, 2017 at 3:27 PM, David Malcolm > wrote: > > * cp-tree.h (struct saved_scope): Add "location" field. > > saved_scope seems like the wrong place for this; it's only > interesting > at parse time,

Re: Prevent invalid register mode changes in combine

On 09/18/2017 05:38 AM, Richard Sandiford wrote: > This patch stops combine from changing the mode of an existing register > in-place if doing so would change the size of the underlying register > allocation size, as given by REGMODE_NATURAL_SIZE. Without this, > many tests fail in

Re: Clobbers and Scratch Registers

On 08/21/2017 10:11 PM, Alan Modra wrote: > On Mon, Aug 21, 2017 at 06:33:09PM +0100, Richard Sandiford wrote: >> I think it's worth emphasising that tying operands doesn't change >> whether an output needs an earlyclobber or not. E.g. for: > > Thanks for noticing this. It turns out that my

Re: [PATCH] Asm memory constraints

On 08/20/2017 06:59 PM, Alan Modra wrote: > On Sun, Aug 20, 2017 at 08:00:53AM -0500, Segher Boessenkool wrote: >> Hi Alan, >> >> On Sat, Aug 19, 2017 at 12:19:35AM +0930, Alan Modra wrote: >>> +Flushing registers to memory has performance implications and may be >>> +an issue for time-sensitive

[patch, fortran] New take on PR 82373

Hello world, after some thought, I think the PR can be fixed by something far less invasive than my previous patch. The new version of the patch simply issues an error for a non-printable character (which should never be legal). Anything else should be caught by other error reporting routines.

Re: Make more use of subreg_size_lowpart_offset

On 08/23/2017 04:52 AM, Richard Sandiford wrote: > This patch uses subreg_size_lowpart_offset in places that open-coded > the calculation. The reload use (and the LRA one that was based on it) > seemed to ignore the BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN case; it's not > obvious whether that was

Minor tree-ssa-dse.c bugfix

While working with Martin L's bugfix/cleanup I came across a minor bug in the DSE code. Specifically it mis-handles references with negative offsets. Example code can be found in gcc.dg/pr48335-4.c. Thankfully these are relatively uncommon and we can just prune them from consideration

Re: [PATCH 1/2] C++: avoid partial duplicate implementation of cp_parser_error

On Wed, 2017-10-11 at 17:18 -0400, Jason Merrill wrote: > On Tue, Sep 26, 2017 at 9:56 AM, David Malcolm > wrote: > > In r251026 (aka 3fe34694f0990d1d649711ede0326497f8a849dc, > > "C/C++: show pertinent open token when missing a close token") > > I copied part of

Re: patch to fix PR82353

On Thu, Oct 12, 2017 at 01:05:21PM -0400, Vladimir Makarov wrote: > > > On 10/12/2017 12:49 PM, Jakub Jelinek wrote: > > Hi! > > > > On Wed, Oct 11, 2017 at 06:41:05PM -0400, Vladimir Makarov wrote: > > > > Tested on x86_64-linux -m32/-m64, and verified with cc1plus before your > > > > change,

Re: patch to fix PR82353

On 10/12/2017 12:49 PM, Jakub Jelinek wrote: Hi! On Wed, Oct 11, 2017 at 06:41:05PM -0400, Vladimir Makarov wrote: Tested on x86_64-linux -m32/-m64, and verified with cc1plus before your change, ok for trunk? BTW, I think it is quite fragile to scan for the reload messages, so I've cooked

Re: patch to fix PR82353

Hi! On Wed, Oct 11, 2017 at 06:41:05PM -0400, Vladimir Makarov wrote: > > Tested on x86_64-linux -m32/-m64, and verified with cc1plus before your > > change, ok for trunk? BTW, I think it is quite fragile to scan for the reload messages, so I've cooked up a runtime test that fails before your

Zen tuning part 7: Fix ix86_adjust_cost

Hi, this patch fixes ix86_adjust_cost for zen support. In particular the original code was accounting memory latencies incorrectly (3 for integer, 2 for FP unit) while they are 4 for integer and 7 for FP on this CPU. Using lower latencies makes scheduler overly pesimistic about CPU's ability to

RE: [PATCH][GCC][AArch64] Dot Product SIMD patterns [Patch (5/8)]

> -Original Message- > From: Richard Earnshaw (lists) [mailto:richard.earns...@arm.com] > Sent: 12 October 2017 13:58 > To: Tamar Christina; James Greenhalgh > Cc: gcc-patches@gcc.gnu.org; nd; Marcus Shawcroft > Subject: Re: [PATCH][GCC][AArch64] Dot Product SIMD patterns [Patch > (5/8)]

Re: [PATCH] Add a warning for invalid function casts

On Thu, 12 Oct 2017, Martin Sebor wrote: > Yes. In light of this discussion I am thinking it might be > worthwhile to bring up the issue of generic function pointers > with WG14 for C2X. I'm fine with the idea of having a standard solution that (unlike void (*) (void)) cannot be called at all

Re: [PATCH] Add a warning for invalid function casts

On 10/12/2017 05:52 AM, Pedro Alves wrote: On 10/11/2017 03:57 AM, Martin Sebor wrote: [X] This can be function that takes an argument of an incomplete type, such as: struct Incomplete; typedef void Uncallable (struct Incomplete); Any function can safely be converted to Uncallable*

Re: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

On 10/12/2017 02:12 AM, Tsimbalist, Igor V wrote: >> Seems reasonable. As a result something like >> check_missing_nocf_check_attribute is going to just go away along with the >> code in *-typeck.c which called it, right? If so that seems like a nice >> cleanup. > Yes, you are right. > >

Re: [PATCH][GRAPHITE] Fix PR82525

On Oct 12, 2017 4:36 AM, "Richard Biener" wrote: The following avoids code-generation errors for modulo operations resulting from our own constraints ending up as no-ops because the type we code-generate in already imposes the modulo operation. For the case in SPEC 2k6

[PATCH, alpha]: Use std::swap some more.

No functional changes. 2017-10-12 Uros Bizjak * config/alpha/alpha.c (alpha_split_conditional_move): Use std::swap instead of manually swapping. (alpha_stdarg_optimize_hook): Ditto. (alpha_canonicalize_comparison): Ditto. Bootstrapped and regression tested

Re: [PATCH][GRAPHITE] Fix PR69728 in "another" way

On Oct 12, 2017 9:08 AM, "Richard Biener" wrote: I made scheduling to fail when we end up with an empty domain but as I forgot to actually check the return value of build_original_schedule the fix was equivalent to just doing nothing to the schedule when it has an empty

Re: [PATCH][GRAPHITE] Lift some IV restrictions

On Oct 12, 2017 9:29 AM, "Richard Biener" wrote: The type check seems premature (we're checking CHRECs already) and we certainly can handle POINTER IVs just fine. Bootstrap / regtest running on x86_64-unknown-linux-gnu. SPEC CPU 2k6 sees ~100 more loop nest optimizations

Re: [PATCH][GRAPHITE] Fix PR82451 (and PR82355 in a different way)

On Oct 11, 2017 9:43 AM, "Richard Biener" wrote: For PR82355 I introduced a fake dimension to ISL to allow CHRECs having an evolution in a loop that isn't fully part of the SESE region we are processing. That was easier than fending off those CHRECs (without simply giving up

[PATCH][GRAPHITE] Lift some IV restrictions

The type check seems premature (we're checking CHRECs already) and we certainly can handle POINTER IVs just fine. Bootstrap / regtest running on x86_64-unknown-linux-gnu. SPEC CPU 2k6 sees ~100 more loop nest optimizations that way. Ok? [I'd rather have problematical testcases for those weird

Re: [PATCH GCC][6/7]Support loop nest distribution for builtin partition

on Sep 17 00:00:00 2001 From: Bin Cheng <binch...@e108451-lin.cambridge.arm.com> Date: Wed, 27 Sep 2017 13:00:59 +0100 Subject: [PATCH 6/7] loop_nest-builtin-pattern-20171012.txt --- gcc/testsuite/gcc.dg/tree-ssa/ldist-28.c | 16 + gcc/testsuite/gcc.dg/tree-ssa/ldist-29.c | 17 ++ gcc/testsui

[PATCH][GRAPHITE] Fix PR69728 in "another" way

I made scheduling to fail when we end up with an empty domain but as I forgot to actually check the return value of build_original_schedule the fix was equivalent to just doing nothing to the schedule when it has an empty domain. I verified that for the testcase it DCEs the relevant stmt and

Re: [PATCH 1/2] add unique_ptr header

On Wed, Oct 11, 2017 at 02:16:38PM -0400, David Malcolm wrote: > On Sat, 2017-08-05 at 01:39 -0400, Trevor Saunders wrote: > > On Fri, Aug 04, 2017 at 08:55:50PM +0100, Jonathan Wakely wrote: > > > On 01/08/17 23:09 -0400, Trevor Saunders wrote: > > > > aiui C++03 is C++98 with a few additions to

RE: [PATCH][GCC][Testsuite][ARM][AArch64] Enable Dot Product for generic tests for ARM and AArch64 [Patch (7/8)]

> -Original Message- > From: Richard Earnshaw (lists) [mailto:richard.earns...@arm.com] > Sent: 12 October 2017 14:21 > To: Tamar Christina; James Greenhalgh > Cc: gcc-patches@gcc.gnu.org; nd; Marcus Shawcroft > Subject: Re: [PATCH][GCC][Testsuite][ARM][AArch64] Enable Dot Product > for

Re: [PATCH GCC]Refine comment and set type for partition merged from SCC

On Wed, Oct 11, 2017 at 6:10 PM, Bin Cheng wrote: > Hi, > When reading the code I found it's could be confusing without comment. > This patch adds comment explaining why we want merge PARALLEL type > partitions in a SCC, even though the result partition can no longer > be

Re: [PATCH GCC][7/7]Merge adjacent memset builtin partitions

On Thu, Oct 5, 2017 at 3:17 PM, Bin Cheng wrote: > Hi, > This patch merges adjacent memset builtin partitions if possible. It is > a useful special case optimization transforming below code: > > #define M (256) > #define N (512) > > struct st > { > int a[M][N]; > int c[M];

Re: [PATCH GCC][6/7]Support loop nest distribution for builtin partition

On Thu, Oct 5, 2017 at 3:17 PM, Bin Cheng wrote: > Hi, > This patch rewrites classification part of builtin partition so that nested > builtin partitions are supported. With this extension, below loop nest: > void > foo (void) > { > for (unsigned i = 0; i < M; ++i) > for

Re: [PATCH][GCC][Testsuite][ARM][AArch64] Enable Dot Product for generic tests for ARM and AArch64 [Patch (7/8)]

On 06/10/17 13:45, Tamar Christina wrote: > Hi All, > > this is a respin with the changes suggested. Note that this patch is no 8/8 > in the series. > > Regtested on arm-none-eabi, armeb-none-eabi, > aarch64-none-elf and aarch64_be-none-elf with no issues found. > > Ok for trunk? > >

Re: [PATCH][GCC][ARM] Dot Product NEON patterns [Patch (2/8)]

On 06/10/17 13:44, Tamar Christina wrote: > Hi All, > > this is a minor respin with changes echo'd from feedback from aarch64. > I assume still OK for trunk. > > Regtested on arm-none-eabi, armeb-none-eabi, > aarch64-none-elf and aarch64_be-none-elf with no issues found. > > Ok for trunk? > >

Re: [PATCH][RFC] Instrument function exit with __builtin_unreachable in C++.

On Thu, Oct 12, 2017 at 4:40 AM, Martin Liška wrote: > On 10/11/2017 04:59 PM, Jason Merrill wrote: >> On Thu, Oct 5, 2017 at 12:53 PM, Martin Liška wrote: >>> On 10/05/2017 05:07 PM, Jason Merrill wrote: On Thu, Oct 5, 2017 at 6:31 AM, Martin Liška

Re: [PATCH] Add further VEC_SELECT verification

On Wed, 11 Oct 2017, Jakub Jelinek wrote: > Hi! > > This patch adds verification that vec_select in *.md files > doesn't have any out of bounds indices in the selector. > > Bootstrapped/regtested on x86_64-linux and i686-linux, tested > by building cc1 of aarch64, arm, powerpc64le and s390x

Re: [PATCH] Add a warning for invalid function casts

On 10/11/2017 03:57 AM, Martin Sebor wrote: > > > [X] This can be function that takes an argument of an incomplete > type, such as: > > struct Incomplete; > typedef void Uncallable (struct Incomplete); > > Any function can safely be converted to Uncallable* without > the risk of being

Re: [PATCH] Add a warning for invalid function casts

On 10/11/2017 03:57 AM, Martin Sebor wrote: > > > Incidentally, void(*)(void) in C++ is a poor choice for this > use case also because of the language's default function > arguments. It's an easy mistake for a C++ programmer to make > to assume that given, say: > > void foo (const char *s =

Re: [PATCH] Add a warning for invalid function casts

On 10/11/2017 06:58 PM, Martin Sebor wrote: > On 10/11/2017 11:26 AM, Joseph Myers wrote: >> On Tue, 10 Oct 2017, Martin Sebor wrote: >> >>> The ideal solution for 1) would be a function pointer that can >>> never be used to call a function (i.e., the void* equivalent >>> for functions).[X] >> >>

Re: [PATCH][GRAPHITE] Fix PR82451 (and PR82355 in a different way)

On Thu, Oct 12, 2017 at 12:13 PM, Richard Biener wrote: > On Thu, 12 Oct 2017, Bin.Cheng wrote: > >> On Wed, Oct 11, 2017 at 3:43 PM, Richard Biener wrote: >> > >> > For PR82355 I introduced a fake dimension to ISL to allow CHRECs >> > having an evolution in

Re: [PATCH] Add -fsanitize=pointer-{compare,subtract}.

On Thu, Oct 12, 2017 at 01:30:34PM +0200, Martin Liška wrote: > There's one false positive I've noticed: > > $ cat /tmp/ptr-cmp.c > int > __attribute__((noinline)) > foo(char *p1, char *p2) > { > if (p2 != 0 && p1 > p2) > return 0; > > return 1; > } Guess that is an argument for

Re: patch to fix PR82353

Hello! > The following patch fixes > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82353 > > LRA did not update hard reg liveness on bb borders for hard regs which are > part of insn patterns > like CFLAGS reg. It was ok for inheritance in EBB which creates only moves > and they usually > have

Re: [PATCH] Add -fsanitize=pointer-{compare,subtract}.

On Thu, Oct 12, 2017 at 01:13:56PM +0200, Martin Liška wrote: > + if (a1 == a2) > +return; > + > + uptr shadow_offset1, shadow_offset2; > + bool valid1, valid2; > + { > +ThreadRegistryLock l(()); > + > +valid1 = GetStackVariableBeginning(a1, _offset1); > +valid2 =

Re: [PATCH] Add -fsanitize=pointer-{compare,subtract}.

Hi. There's one false positive I've noticed: $ cat /tmp/ptr-cmp.c int __attribute__((noinline)) foo(char *p1, char *p2) { if (p2 != 0 && p1 > p2) return 0; return 1; } int main(int argc, char **argv) { return foo(argv[0], 0); } $ gcc /tmp/ptr-cmp.c

Re: [PATCH] Add -fsanitize=pointer-{compare,subtract}.

On 10/11/2017 04:22 PM, Jakub Jelinek wrote: > On Wed, Oct 11, 2017 at 03:36:40PM +0200, Martin Liška wrote: >>> std::swap(addr1, addr2); ? I don't see it used in any of libsanitizer >>> though, so not sure if the corresponding STL header is included. >> >> They don't use it anywhere and I had

Re: [PATCH][GRAPHITE] Fix PR82451 (and PR82355 in a different way)

On Thu, 12 Oct 2017, Bin.Cheng wrote: > On Wed, Oct 11, 2017 at 3:43 PM, Richard Biener wrote: > > > > For PR82355 I introduced a fake dimension to ISL to allow CHRECs > > having an evolution in a loop that isn't fully part of the SESE > > region we are processing. That was

Re: [PATCH 2/2] PR libgcc/59714 complex division is surprising on aarch64

On 12/10/17 06:21, vladimir.mezent...@oracle.com wrote: > From: Vladimir Mezentsev > > FMA (floating-point multiply-add) instructions are supported on aarch64. > These instructions can produce different result if two operations executed > separately. >

Re: [PATCH][GRAPHITE] Fix PR82451 (and PR82355 in a different way)

On Wed, Oct 11, 2017 at 3:43 PM, Richard Biener wrote: > > For PR82355 I introduced a fake dimension to ISL to allow CHRECs > having an evolution in a loop that isn't fully part of the SESE > region we are processing. That was easier than fending off those > CHRECs (without

[PATCH][GRAPHITE] Fix PR82525

The following avoids code-generation errors for modulo operations resulting from our own constraints ending up as no-ops because the type we code-generate in already imposes the modulo operation. For the case in SPEC 2k6 triggering this we'd even know the modulo constraint isn't necessary - we

Re: [PATCH][RFC] Instrument function exit with __builtin_unreachable in C++.

On Thu, Oct 12, 2017 at 10:40:42AM +0200, Martin Liška wrote: > --- a/gcc/cp/constexpr.c > +++ b/gcc/cp/constexpr.c > @@ -1175,7 +1175,12 @@ cxx_eval_builtin_function_call (const constexpr_ctx > *ctx, tree t, tree fun, > { > new_call = build_call_array_loc (EXPR_LOCATION (t),

Re: [PATCH][RFC] Instrument function exit with __builtin_unreachable in C++.

On 10/11/2017 04:59 PM, Jason Merrill wrote: > On Thu, Oct 5, 2017 at 12:53 PM, Martin Liška wrote: >> On 10/05/2017 05:07 PM, Jason Merrill wrote: >>> On Thu, Oct 5, 2017 at 6:31 AM, Martin Liška wrote: As discussed 2 days ago on IRC with Jakub and Jonathan,

Re: [PATCH] Improve x86 and + rotate (PR target/82498)

On Thu, Oct 12, 2017 at 10:32 AM, Jakub Jelinek wrote: > On Thu, Oct 12, 2017 at 08:32:32AM +0200, Uros Bizjak wrote: >> On Wed, Oct 11, 2017 at 10:59 PM, Jakub Jelinek wrote: >> > As can be seen on the testcase below, the *3_mask >> > insn/splitter is able to

Re: [PATCH] Improve x86 and + rotate (PR target/82498)

On Thu, Oct 12, 2017 at 08:32:32AM +0200, Uros Bizjak wrote: > On Wed, Oct 11, 2017 at 10:59 PM, Jakub Jelinek wrote: > > As can be seen on the testcase below, the *3_mask > > insn/splitter is able to optimize only the case when the and is > > performed in SImode and then the

RE: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

> Seems reasonable. As a result something like > check_missing_nocf_check_attribute is going to just go away along with the > code in *-typeck.c which called it, right? If so that seems like a nice > cleanup. Yes, you are right. Updated patch is attached. Igor > -Original Message- >

Re: [PATCH] Improve x86 and + rotate (PR target/82498)

On Thu, Oct 12, 2017 at 8:39 AM, Uros Bizjak wrote: > On Thu, Oct 12, 2017 at 8:32 AM, Uros Bizjak wrote: >> On Wed, Oct 11, 2017 at 10:59 PM, Jakub Jelinek wrote: >>> Hi! >>> >>> As can be seen on the testcase below, the *3_mask >>>

Re: [PATCH] Improve x86 and + rotate (PR target/82498)

On Thu, Oct 12, 2017 at 8:32 AM, Uros Bizjak wrote: > On Wed, Oct 11, 2017 at 10:59 PM, Jakub Jelinek wrote: >> Hi! >> >> As can be seen on the testcase below, the *3_mask >> insn/splitter is able to optimize only the case when the and is >> performed in

Re: [PATCH] Improve x86 and + rotate (PR target/82498)

On Wed, Oct 11, 2017 at 10:59 PM, Jakub Jelinek wrote: > Hi! > > As can be seen on the testcase below, the *3_mask > insn/splitter is able to optimize only the case when the and is > performed in SImode and then the result subreged into QImode, > while if the computation is

Re: Make more use of subreg_lowpart_offset

On 08/23/2017 04:51 AM, Richard Sandiford wrote: > This patch uses subreg_lowpart_offset in places that open-coded > the calculation. It also uses it in regcprop.c to test whether, > after a mode change, the first register in a multi-register group > is still the right one. > > Tested on

Re: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

On 10/05/2017 04:20 AM, Tsimbalist, Igor V wrote: > I would like to implement the patch in a bit different way depending on > answers I will get for > my following proposals: > > - I propose to make a type with 'nocf_check' attribute to be different from > type w/o the attribute. >The