21114(define_insn_and_split "ssse3_palignrdi"
21115 [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
21116(unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
21117(match_operand:DI 2 "register_mmxmem_operand"
"ym,x,Yv")
21118
on 2022/6/6 18:01, Richard Sandiford wrote:
> "Kewen.Lin" writes:
>> Hi,
>>
>> r10-3912 updated the format of VECTOR_MODES_WITH_PREFIX by
>> adding one more parameter ORDER, the related document is out
>> of date. So update the document for ORDER.
>>
>> Is it ok for trunk?
>>
>> BR,
>> Kewen
>>
If -mcpu or -march is specified and there is no -mabi, we will calculate
default ABI from arch string provided by -march or defined in CPU info.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (compute_default_abi):
Implementation
to calculate -mabi from arch string.
Hi Will,
The whole series looks good to me, thanks! IMHO one place can be
further refactored, not sure if it's worth to updating together in
this series, it's ...
on 2022/6/7 06:05, will schmidt wrote:
> [PATCH,RS6000 2/5) Rework the RS6000_BTM defines.
>
> The RS6000_BTM_ definitions are
Hi,
On 2/6/2022 上午 5:01, Segher Boessenkool wrote:
> Hi!
>
> Some more nitpicking...
>
> On Wed, May 18, 2022 at 04:52:26PM +0800, HAO CHEN GUI wrote:
>>const double __builtin_vsx_xsmaxdp (double, double);
>> -XSMAXDP smaxdf3 {}
>> +XSMAXDP fmaxdf3 {}
>>
>>const double
[PATCH 3/3] Adjust MMA tests to account for no store vector pair.
In changing the default for generating the store vector pair instructions,
I had to adjust several of the MMA tests to remove checking for these
instructions. Mostly I just deleted the scan-assembler lines checking for
stxvp. In
[PATCH 2/3] Disable generating load/store vector pairs for block copies.
If the store vector pair instruction is disabled, do not generate block
copies that use load and store vector pair instructions.
I have built bootstrap compilers and run the regression tests on three
different systems:
[PATCH 1/3] Disable generating store vector pair.
Testing has revealed that the power10 has some slowdowns if the store
vector pair instruction is generated in some cases. This patch disables
generating the store vector pair instructions (stxvp, pstxvp, and stxvpx)
unless an undocumented switch
[PATCH 0/3] Disable generating store vector pair.
Testing has revealed that the power10 has some slowdowns if the store vector
pair instruction is generated in some cases. This patch disables generating
the store vector pair instructions (stxvp, pstxvp, and stxvpx) unless an
undocumented switch
Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293.
This is version 3 of the patch. The original patch was:
| Date: Mon, 28 Mar 2022 12:26:02 -0400
| Subject: [PATCH 1/4] Optimize vec_splats of constant vec_extract for
V2DI/V2DF, PR target 99293.
| Message-ID:
|
On Thu, 2022-06-02 at 21:23 -0400, Antoni Boucher via Gcc-patches
wrote:
> Sorry, forgot to attach the patch.
>
> Here it is.
>
> On Thu, 2022-06-02 at 21:20 -0400, Antoni Boucher via Jit wrote:
> > Hi.
> > The attached patch fix bug 105827:
> >
On Mon, 2022-05-30 at 18:09 +0800, Xi Ruoyao wrote:
> Ping. I'd like to see libgccjit working on LoongArch so I would be
> able
> to submit a Rust port to upstream.
>
> If the result is NACK I'd like to know alternative approaches to fix
> the
> build failure.
>
> I doubt if "j...@gcc.gnu.org"
On Fri, 3 Jun 2022, Marek Polacek via Gcc-patches wrote:
> However, the patch does not touch the C FE. The C FE doesn't have
> a counterpart to C++'s cp_parser_attributes_opt -- it only has
> c_parser_transaction_attributes (which parses both GNU and [[]]
> attributes), but that's TM-specific.
This patch is the initial implementation of OpenMP-API specs book section
20.5.5 with title "Thread Handles"
libgomp/ChangeLog
2022-05-06 Ahmed Sayed
* Makefile.am (libgompd_la_SOURCES): Add ompd-threads.c.
* Makefile.in: Regenerate.
* ompd-support.h ( gompd_thread_initial_tls_bias ): New
On Thu, 2022-06-02 at 23:09 -0400, Antoni Boucher via Gcc-patches
wrote:
> Hi.
> The attached patch fix bug 105829:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105829
>
> Thanks for the review.
> diff --git a/gcc/jit/libgccjit.cc b/gcc/jit/libgccjit.cc
> index cc6486c9cad..12e7679988b 100644
[PATCH,RS6000 4/5] Replace MASK_ with OPTION_MASK_
This replaces the MASK_ references with OPTION_MASK_
and removes the now unused defines.
This patch removes the defines for
MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP,
MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD,
[PATCH,RS6000 5/5] Replace MASK_ usage with OPTION_MASK_
This continues the changes of replacing the MASK_ defines
with their OPTION_MASK_ equivalents.
This patch removes the defines for
MASK_P8_VECTOR, MASK_P9_VECTOR, MASK_P9_MISC, MASK_POPCNTB,
MASK_POPCNTD, MASK_PPC_GFXOPT, MASK_PPC_GPOPT,
[PATCH, RS6000 3/5] Rework the RS6000_BTM defines, continued.
The RS6000_BTM_ definitions are mostly unused after
the rs6000 builtin code was reworked. This cleans
up the remaining RS6000_BTM_ references by replacing
them with their OPTION_MASK_ equivalents.
This patch removes the defines
[PATCH,RS6000 2/5) Rework the RS6000_BTM defines.
The RS6000_BTM_ definitions are mostly unused after the rs6000
builtin code was reworked. The remaining references can be replaced
with the OPTION_MASK_ and MASK_ equivalents.
This patch remvoes the defines:
RS6000_BTM_FRES, RS6000_BTM_FRSQRTE,
[PATCH,RS6000 1/5] Clean-up MASK_ and RS6000_BTM_ definitions.
Hi,
This patch removes the defines that are no longer used, and
updates the comment for the set of MASK_ defines.
This patch removes the defines for
MASK_REGNAMES, MASK_PROTOTYPE, RS6000_BTM_ALWAYS, RS6000_BTM_COMMON.
gcc/
Hi,
This series cleans up the assorted MASK_, OPTION_MASK_,
and RS6000_BTM_ defines that we have sprinkled through the
rs6000 target code.
The MASK_ entries are currently defined as their OPTION_MASK_
equivalents since their introduction when the rs6000_isa_flags was
added via commit
Hello-
The attached patch upgrades the cpp_wcwidth() function (needed for
computing display columns in diagnostics output) from Unicode 13 to
Unicode 14. I just mechanically followed the procedure in
contrib/unicode/README with nothing unexpected coming up. I attached it
compressed since it's a
On 6/6/22 15:39, Michael Colavita via Gcc-patches wrote:
Per #105787, "using enum" in a dependent context leads to an ICE. This
is because the type substitution logic doesn't properly juggle the
context and abstract origin for CONST_DECLs introduced via using enum.
When we are performing type
Per #105787, "using enum" in a dependent context leads to an ICE. This
is because the type substitution logic doesn't properly juggle the
context and abstract origin for CONST_DECLs introduced via using enum.
When we are performing type substitution on the CONST_DECL, we want to
do so in the
On 6/6/22 14:27, Patrick Palka wrote:
On Thu, 7 Oct 2021, Jason Merrill wrote:
On 10/7/21 11:17, Patrick Palka wrote:
On Wed, 6 Oct 2021, Jason Merrill wrote:
On 10/6/21 15:52, Patrick Palka wrote:
On Wed, 6 Oct 2021, Patrick Palka wrote:
On Tue, 5 Oct 2021, Jason Merrill wrote:
On
On Sun, Jun 5, 2022 at 7:27 PM Hongtao Liu via Gcc-patches
wrote:
>
> On Mon, Jun 6, 2022 at 3:17 AM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Thu, Jun 2, 2022 at 5:04 PM Jan Beulich wrote:
> > >
> > > The 64-bit, 128-bit, and 512-bit variants have VDI return type, in
> > > line with
On 6/5/22 06:09, Roger Sayle wrote:
Hi Jason,
My apologies for the long delay, but I've finally got around to
implementing your suggested improvements (implied by your review):
https://gcc.gnu.org/pipermail/gcc-patches/2022-March/591504.html
of my patch for PR c++/96442:
On Thu, 7 Oct 2021, Jason Merrill wrote:
> On 10/7/21 11:17, Patrick Palka wrote:
> > On Wed, 6 Oct 2021, Jason Merrill wrote:
> >
> > > On 10/6/21 15:52, Patrick Palka wrote:
> > > > On Wed, 6 Oct 2021, Patrick Palka wrote:
> > > >
> > > > > On Tue, 5 Oct 2021, Jason Merrill wrote:
> > > > >
On Mon, Jun 06, 2022 at 07:32:31PM +0200, Mohamed Atef wrote:
> So for both cases one should read the value of *team and if it's NULL, the
> function returns some error state (eg. ompd_rc_unavailable)
No, I think for team NULL it should simply push something different
to ompd_parallel_handle_t,
On Mon, Jun 06, 2022 at 05:13:24PM +0200, Mohamed Sayed via Gcc-patches wrote:
> > 2022-06-06 Mohamed Sayed
> >
> >
> > * Makefile.am: (libgompd_la_SOURCES): Add ompd-parallel.c.
The ChangeLog formatting is wrong. The above line should be:
* Makefile.am (libgompd_la_SOURCES): Add
في الاثنين، ٦ يونيو، ٢٠٢٢ ٧:١٣ م Jakub Jelinek via Gcc-patches <
gcc-patches@gcc.gnu.org> كتب:
> On Mon, Jun 06, 2022 at 01:48:22AM +0200, Mohamed Sayed via Gcc-patches
> wrote:
> > This patch adds parallel region handles specified in section 5.5.3.
> > >From examining libgomp code, I found that
> > Patches attached. They already incorporated the .cc rename, now
> > rebased to be after the change to tree.h
>
> @@ -1412,8 +1412,7 @@ vect_recog_widen_op_pattern (vec_info *vinfo,
>2, oprnd, half_type, unprom, vectype);
>
>tree var = vect_recog_temp_ssa_var
On Mon, Jun 06, 2022 at 01:48:22AM +0200, Mohamed Sayed via Gcc-patches wrote:
> This patch adds parallel region handles specified in section 5.5.3.
> >From examining libgomp code, I found that struct gomp_team describes the
> parallel region.
I think it would be nice to first find out what the
On 27/05/2022 20:16, Thomas Schwinge wrote:
Hi Andrew!
On 2022-05-24T16:27:52+0100, Andrew Stubbs wrote:
I've committed this patch to set the minimum required LLVM version, for
the assembler and linker, to 13.0.1. An upgrade from LLVM 9 is a
prerequisite for the gfx90a support, and 13.0.1 is
Hi Roger,
>> I just tried this on i386-pc-solaris2.11: unfortunately, it made no
> difference.
>
> Awesome! Very many thanks for trying this. Alas it confirms that the patch
> I'm currently spinning won't have any affect. So by a process of
> elimination,
> the miscompilation must be triggered
This is the final diff
On Mon, Jun 6, 2022 at 1:48 AM Mohamed Sayed
wrote:
> This patch adds parallel region handles specified in section 5.5.3.
> From examining libgomp code, I found that struct gomp_team describes the
> parallel region.
> The Thread handle gives the address of gomp_thread so,
Hi jasonwucj,
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Chung-Ju Wu
> via Gcc-patches
> Sent: Thursday, May 26, 2022 8:18 AM
> To: Richard Earnshaw ; gcc-patches patc...@gcc.gnu.org>
> Cc: jason...@anshingtek.com.tw
> Subject:
Hi jasonwucj,
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Chung-Ju Wu
> via Gcc-patches
> Sent: Thursday, May 26, 2022 8:18 AM
> To: Richard Earnshaw ; gcc-patches patc...@gcc.gnu.org>
> Cc: jason...@anshingtek.com.tw
> Subject:
Hi jasonwucj,
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Chung-Ju Wu
> via Gcc-patches
> Sent: Thursday, May 26, 2022 8:19 AM
> To: Richard Earnshaw ; gcc-patches patc...@gcc.gnu.org>
> Cc: jason...@anshingtek.com.tw
> Subject:
This patch fixes both ICE regressions PR middle-end/105853 and
PR target/105856 caused by my recent patch to expand small const structs
as immediate constants. That patch updated code generation in three
places: two in expr.cc that call store_constructor directly, and the
third in calls.cc's
On Mon, Jun 06, 2022 at 09:38:30PM +0800, Chung-Lin Tang wrote:
> I'll file a bugzilla for the target construct.
Thanks.
> That said, can we delay FIELD_DECL support for uses_allocators? (which is
> target construct only)
> Since it appears to be not trivial at the moment.
Sure.
But would be
On 2022/6/6 9:22 下午, Jakub Jelinek wrote:
On Mon, Jun 06, 2022 at 09:19:18PM +0800, Chung-Lin Tang wrote:
On 2022/5/31 6:02 PM, Jakub Jelinek wrote:
5) for C++, we should handle FIELD_DECLs, but it shouldn't be hard, just
look how it is handled for private too
Jakub
About
On Mon, Jun 06, 2022 at 09:19:18PM +0800, Chung-Lin Tang wrote:
> On 2022/5/31 6:02 PM, Jakub Jelinek wrote:
> > 5) for C++, we should handle FIELD_DECLs, but it shouldn't be hard, just
> > look how it is handled for private too
> >
> > Jakub
>
> About private() for non-static members,
On 2022/5/31 6:02 PM, Jakub Jelinek wrote:
5) for C++, we should handle FIELD_DECLs, but it shouldn't be hard, just
look how it is handled for private too
Jakub
About private() for non-static members, is it really working right now?
A simple test:
struct C {
Hi Rainer,
> > The one experiment I'd like to be able to try, to investigate the
> > cause/cure of this, is:
> >
> > diff --git a/gcc/calls.cc b/gcc/calls.cc index a4336c1..05fdd24 100644
> > --- a/gcc/calls.cc
> > +++ b/gcc/calls.cc
> > @@ -2177,7 +2177,7 @@ load_register_parameters (struct
Andreas Schwab writes:
> On Jun 06 2022, Roger Sayle wrote:
>
>> gcc -std=gnu99 -c -g -gnatpg -gnatwns -gnata -W -Wall -I- -I.
>> -Iada/generated -Iada -I../../gcc/gcc/ada ../../gcc/gcc/ada/osint.adb -o
>> ada/osint.o
>> osint.adb:438:31: "strlen" not declared in "CRTL"
>> osint.adb:441:14:
Hi Roger,
> My sincere apologies for the breakage. I'm currently regression testing a
> solution to the ICEs introduced by my "small const struct" patch, which
> fingers-crossed might also fix this Ada bootstrap. For a while when
> Rainer also reported the bootstrap failure is visible, on
>
On Jun 06 2022, Roger Sayle wrote:
> Hi Andreas,
>> > gcc -std=gnu99 -c -g -gnatpg -gnatwns -gnata -W -Wall -I- -I.
>> > -Iada/generated -Iada -I../../gcc/gcc/ada ../../gcc/gcc/ada/osint.adb
>> > -o ada/osint.o
>> > osint.adb:438:31: "strlen" not declared in "CRTL"
>> > osint.adb:441:14:
On Sun, Jun 5, 2022 at 7:19 PM Roger Sayle wrote:
>
>
> This patch extends the recent and;cmp to not;test optimization to also
> perform this transformation for TImode on TARGET_64BIT and DImode on -m32,
> One motivation for this is that it's a step to fixing the current failure
> of
Hi Andreas,
> > gcc -std=gnu99 -c -g -gnatpg -gnatwns -gnata -W -Wall -I- -I.
> > -Iada/generated -Iada -I../../gcc/gcc/ada ../../gcc/gcc/ada/osint.adb
> > -o ada/osint.o
> > osint.adb:438:31: "strlen" not declared in "CRTL"
> > osint.adb:441:14: "strncpy" not declared in "CRTL"
> >
On Jun 06 2022, Roger Sayle wrote:
> gcc -std=gnu99 -c -g -gnatpg -gnatwns -gnata -W -Wall -I- -I.
> -Iada/generated -Iada -I../../gcc/gcc/ada ../../gcc/gcc/ada/osint.adb -o
> ada/osint.o
> osint.adb:438:31: "strlen" not declared in "CRTL"
> osint.adb:441:14: "strncpy" not declared in "CRTL"
>
Prathamesh Kulkarni writes:
>> > {
>> >/* The pattern matching functions above are written to look for a small
>> > number to begin the sequence (0, 1, N/2). If we begin with an index
>> > @@ -24084,6 +24112,12 @@ aarch64_expand_vec_perm_const_1 (struct
>> > expand_vec_perm_d *d)
>>
On Sun, Jun 5, 2022 at 7:19 PM Roger Sayle wrote:
>
>
> This patch extends the recent and;cmp to not;test optimization to also
> perform this transformation for TImode on TARGET_64BIT and DImode on -m32,
> One motivation for this is that it's a step to fixing the current failure
> of
"Kewen.Lin" writes:
> Hi,
>
> r10-3912 updated the format of VECTOR_MODES_WITH_PREFIX by
> adding one more parameter ORDER, the related document is out
> of date. So update the document for ORDER.
>
> Is it ok for trunk?
>
> BR,
> Kewen
> -
>
> gcc/ChangeLog:
>
> * machmode.def
On Mon, Jun 6, 2022 at 2:12 AM Hongbo Liu via Gcc-patches
wrote:
>
> Hi,
>
> This is my first time using email patch, please correct me if there is any
> error. Thanks!
>
>
> I found a c++ optimization bug first introduced via
> commit520d5ad337eaa15860a5a964daf7ca46cf31c029, which will make
Fix the ASAN shadow offset hook for the n32 ABI.
gcc/ChangeLog:
* config/mips/mips.cc (mips_asan_shadow_offset): Reformat
to handle the N32 ABI.
* config/mips/mips.h (SUBTARGET_SHADOW_OFFSET): Remove
the macro, as it is not needed anymore.
---
On Mon, Jun 6, 2022 at 10:23 AM Roger Sayle wrote:
>
>
> Hi Uros,
> > > The major theme of this patch is to generalize many of i386.md's
> > > *di3_doubleword patterns to become *_doubleword patterns, i.e.
> > > whenever there exists a "double word" optimization for DImode with
> > > -m32, there
Hi,
This is my first time using email patch, please correct me if there is any
error. Thanks!
I found a c++ optimization bug first introduced via
commit520d5ad337eaa15860a5a964daf7ca46cf31c029, which will make program
compiled with -O2 have unexpected behavior.
How to produce
1. Checkout
Richard Biener writes:
> On Sat, May 21, 2022 at 5:31 PM Roger Sayle
> wrote:
>> This patch simplifies vec_unpack_hi_expr/vec_unpack_lo_expr of a uniform
>> constructor or vec_duplicate operand. The motivation is from PR 105621
>> where after optimization, we're left with:
>>
>> vect_cst__21
On Mon, Jun 6, 2022 at 3:29 PM wrote:
>
> From: yulong
>
> We changed the RTL mode and builtins format about zicbom and zicboz
> subextensions.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed
> "RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
> *
Hi,
Gentle ping https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595209.html
BR,
Kewen
on 2022/5/18 22:07, Kewen.Lin via Gcc-patches wrote:
> Hi,
>
> As PR103353 shows, we may want to continue to expand a MMA built-in
> function like a normal function, even if we have already emitted
> error
Hi,
Gentle ping https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595209.html
BR,
Kewen
on 2022/5/18 22:07, Kewen.Lin via Gcc-patches wrote:
> Hi,
>
> As PR104482 shown, it's one regression about the handlings when
> the argument number is more than the one of built-in function
> prototype.
Hi,
Gentle ping https://gcc.gnu.org/pipermail/gcc-patches/2022-May/594699.html
BR,
Kewen
on 2022/5/13 13:29, Kewen.Lin via Gcc-patches wrote:
> Hi,
>
> PR105485 exposes that new builtin function framework doesn't handle
> unresolved overloaded builtin function well. With new builtin
>
Hi Haochen,
on 2022/6/6 10:21, HAO CHEN GUI wrote:
> Hi,
> This patch replaces shift and ior insns with one rotate and mask
> insn for the split patterns which are for DI byte swap on Power6 and
> before. The test cases shows the optimization.
Nit: I noticed two splitting which are updated in
Hi Rainer (and Andreas),
My sincere apologies for the breakage. I'm currently regression testing a
solution to the ICEs introduced by my "small const struct" patch, which
fingers-crossed might also fix this Ada bootstrap. For a while when
Rainer also reported the bootstrap failure is visible,
Hi Uros,
> > The major theme of this patch is to generalize many of i386.md's
> > *di3_doubleword patterns to become *_doubleword patterns, i.e.
> > whenever there exists a "double word" optimization for DImode with
> > -m32, there should be an equivalent TImode optimization on TARGET_64BIT.
>
On 2/6/2022 下午 5:04, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jun 02, 2022 at 01:30:04PM +0800, HAO CHEN GUI wrote:
>> Segher,
>> Does BCD comparison return false when either operand is invalid coding?
>
> It sets all of LT, GT, and EQ to 0 (it normally sets exactly one of them
> to 1).
From: yulong
We changed the RTL mode and builtins format about zicbom and zicboz
subextensions.
gcc/ChangeLog:
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed
"RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
* config/riscv/riscv-ftypes.def (0): deleted
Hi,
r10-3912 updated the format of VECTOR_MODES_WITH_PREFIX by
adding one more parameter ORDER, the related document is out
of date. So update the document for ORDER.
Is it ok for trunk?
BR,
Kewen
-
gcc/ChangeLog:
* machmode.def (VECTOR_MODES_WITH_PREFIX): Update document for
Hi,
PR105459 exposes one issue in inline_call handling that when it
decides to copy FP flags from callee to caller and rebuild the
optimization node for caller fndecl, it's possible that the target
option node is also necessary to be rebuilt. Without updating
target option node early, it can
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