Hi,
We know that for struct variable assignment, memory copy may be used.
And for memcpy, we may load and store more bytes as possible at one time.
While it may be not best here:
1. Before/after stuct variable assignment, the vaiable may be operated.
And it is hard for some optimizations to leap o
>
> On 10/20/22 19:52, Cui, Lili via Gcc-patches wrote:
> > Hi Honza,
> >
> > Gentle ping
> > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601934.html
> >
> > gcc/ChangeLog
> >
> >* ipa-inline-analysis.cc (do_estimate_edge_time): Add function attribute
> >judgement for INLINE_H
Hi, since these RVV testcases doesn't necessary need abi configuration.
I fix these testcase in this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604642.html
Plz, verify it and merge it. Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2022-10-30 19:02
To: juzhe.zhong
Hi, since these RVV testcases doesn't necessary need abi configuration.
I fix these testcase in this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604642.html
Plz, verify it and merge it. Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2022-10-30 19:00
To: juzhe.zhong
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
* gcc.target/riscv/rvv/base/abi-3.c: Ditto.
* gcc.target/riscv/rvv/base/abi-4.c: Ditto.
* gcc.target/riscv/rvv/base/abi-5.c: Ditto.
* gcc.target/riscv/
This patch doens't handle variable count since it require 5 insns to
be combined to get wanted pattern, but current pass_combine only
supports at most 4.
This patch doesn't handle 16-bit shrd/shld either.
Ideally, we can avoid redundancy of
*x86_64_shld_shrd_1_nozext/*x86_shld_shrd_1_nozext
if mid
>You have a couple of other patterns where operand 1 is matched to
>produce vmovddup insn. These are *avx512f_unpcklpd512 and
>avx_unpcklpd256. You can also remove expander in both
>cases.
Yes, changed in V2 patch.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
Matching
> -Original Message-
> From: Kong, Lingling
> Sent: Friday, October 28, 2022 4:57 PM
> To: Hongtao Liu
> Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org; Jiang,
> Haochen
> Subject: RE: [PATCH 4/6] Support Intel AVX-NE-CONVERT
>
> Hi,
>
> Because we switch intrinsics for avx512bf16 to th
Le 30/10/2022 à 20:23, Mikael Morin a écrit :
Another probable issue is your change to create_function_arglist changes
arglist/hidden_arglist without also changing typelist/hidden_typelist
accordingly. I think a change to gfc_get_function_type is also
necessary: as the function decl is changed
Le 30/10/2022 à 20:23, Mikael Morin a écrit :
I think some discrepancy remains, as gfc_conv_procedure_call accumulates
coarray stuff into the stringargs, while your change accumulates the
associated parameter decls separately into hidden_arglist. It's not
completely clear to me whether it is
Le 28/10/2022 à 22:12, Harald Anlauf via Fortran a écrit :
Dear all,
the passing of procedure arguments in Fortran sometimes requires
ancillary parameters that are "hidden". Examples are string length
and the presence status of scalar variables with optional+value
attribute.
The gfortran ABI i
On Sun, Oct 30, 2022 at 04:22:34PM +0100, Mark Wielaard wrote:
> Hi,
>
> On Wed, Oct 26, 2022 at 10:39:09AM +0200, Jakub Jelinek wrote:
> > I must say I don't understand nor like this DW_LANG_Rust_old stuff at all.
> > Other languages don't do similar dances.
> > Look for D, or Go. Neither of the
Hi,
On Wed, Oct 26, 2022 at 10:39:09AM +0200, Jakub Jelinek wrote:
> I must say I don't understand nor like this DW_LANG_Rust_old stuff at all.
> Other languages don't do similar dances.
> Look for D, or Go. Neither of them has any non-standard lang code as
> fallback, they use the DWARF assigned
On Okt 17 2022, juzhe.zh...@rivai.ai wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vsetvl-1.c: New test.
This fails if the ilp32d ABI is not available.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"An
On Okt 24 2022, juzhe.zh...@rivai.ai wrote:
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
> create mode 100644 gcc/testsuite/gcc.ta
On Okt 20 2022, jiawei wrote:
> diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
> b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
> new file mode 100644
> index 000..90172b57e05
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
> @@ -0,0 +1,10 @@
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