Tamar Christina writes:
>> -Original Message-
>> From: Richard Biener
>> Sent: Tuesday, November 22, 2022 10:59 AM
>> To: Richard Sandiford
>> Cc: Tamar Christina via Gcc-patches ; Tamar
>> Christina ; Richard Biener
>> ; nd
>> Subject: Re: [PATCH 1/8]middle-end: Recognize scalar
Hi,
when two arrays of scalars have a different storage order in Ada, the
front-end makes sure that the conversion is performed component-wise
so that each component can be reversed. So it's a little bit counter
productive that the ldist pass performs the opposite transformation
and synthesizes
The SSA propagator is missing abnormal cleanup which shows in a
sanity check in the uninit engine (and missed CFG verification).
The following adds that.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/107803
* tree-ssa-propagate.cc
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, November 22, 2022 10:59 AM
> To: Richard Sandiford
> Cc: Tamar Christina via Gcc-patches ; Tamar
> Christina ; Richard Biener
> ; nd
> Subject: Re: [PATCH 1/8]middle-end: Recognize scalar reductions from
> bitfields and
On Tue, 22 Nov 2022, Richard Sandiford wrote:
> Tamar Christina via Gcc-patches writes:
> >> So it's not easily possible the within current infrastructure. But it
> >> does look
> >> like ARM might eventually benefit from something like STV on x86?
> >>
> >
> > I'm not sure. The problem with
Christophe Lyon via Gcc-patches writes:
> gcc.target/aarch64/aapcs64/test_dfp_17.c has been failing on
> big-endian, because the _Decimal32 on-stack argument is not padded in
> the same direction depending on endianness.
>
> This patch fixes the testcase so that it expects the argument in the
>
Hi,
> -Original Message-
> From: Philipp Tomsich
> Sent: Tuesday, November 22, 2022 10:35 AM
> To: Tamar Christina
> Cc: Richard Biener ; mtsamis
> ; GCC Patches ;
> jiangning@amperecomputing.com
> Subject: Re: [PATCH] Add pattern to convert vector shift + bitwise and +
> multiply
Christophe Lyon writes:
> On 11/17/22 17:37, Andrea Corallo via Gcc-patches wrote:
>> From: Stam Markianos-Wright
>> In the past we had only defined the vsubq_x generic overload of the
>> vsubq_x_* intrinsics for float vector types. This would cause them
>> to fall back to the `__ARM_undef`
Tested x86_64-linux, Pushed to trunk. Backports will follow.
-- >8 --
The array of pool sizes was previously adjusted to work for msp430-elf
which has 16-bit int and either 16-bit size_t or 20-bit size_t. The
largest pool sizes were disabled unless size_t has more than 20 bits.
The H8 family
Tamar Christina via Gcc-patches writes:
>> So it's not easily possible the within current infrastructure. But it does
>> look
>> like ARM might eventually benefit from something like STV on x86?
>>
>
> I'm not sure. The problem with trying to do this in RTL is that you'd have
> to be
> able
Hi Richard,
> I guess an obvious question is: if 1 (rather than 2) was the right value
> for cores with 2 FMA pipes, why is 4 the right value for cores with 4 FMA
> pipes? It would be good to clarify how, conceptually, the core property
> should map to the fma_reassoc_width value.
1 turns off
Richard & Tamar,
On Fri, 26 Aug 2022 at 15:29, Tamar Christina wrote:
>
> > -Original Message-
> > From: Gcc-patches > bounces+tamar.christina=arm@gcc.gnu.org> On Behalf Of Richard
> > Biener via Gcc-patches
> > Sent: Friday, August 26, 2022 10:08 AM
> > To: mtsamis
> > Cc: GCC
> Am 22.11.2022 um 10:49 schrieb Yixuan Chen :
>
> gcc/testsuite/ChangeLog:
>
> Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.
Ok.
Richard
> 2022-11-22 Yixuan Chen
>
>* gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays"
> option, add "-w"
On 11/17/22 17:37, Andrea Corallo via Gcc-patches wrote:
From: Stam Markianos-Wright
In the past we had only defined the vsubq_x generic overload of the
vsubq_x_* intrinsics for float vector types. This would cause them
to fall back to the `__ARM_undef` failure state if they was called
gcc/testsuite/ChangeLog:
Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.
2022-11-22 Yixuan Chen
* gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays"
option, add "-w" option.
---
gcc/testsuite/gcc.dg/pr106397.c | 1 +
1 file changed, 1 insertion(+)
I noticed the option is ignored because @DO_LINK_MUTEX@
is not defined in d/Make-lang.in.
Tested locally before and after the patch.
Ready to be installed?
Thanks,
Martin
gcc/ChangeLog:
* Makefile.in: Set DO_LINK_MUTEX.
gcc/d/ChangeLog:
* Make-lang.in: Use it as
Hi!
The following patch fixes multiple bugs in warn_for_sign_compare related to
the BIT_NOT_EXPR related warnings.
My understanding is that what those 3 warnings are meant to warn (since 1995
apparently) is the case where we have BIT_NOT_EXPR of a zero-extended
value, so in result_type the value
On Tue, Nov 22, 2022 at 10:04 AM Aldy Hernandez wrote:
>
>
>
> On 11/22/22 09:25, Richard Biener wrote:
> > On Tue, Nov 22, 2022 at 9:24 AM Richard Biener
> > wrote:
> >>
> >> On Mon, Nov 21, 2022 at 5:49 PM Jeff Law wrote:
> >>>
> >>>
> >>> On 11/21/22 09:35, Aldy Hernandez via Gcc-patches
Would it be possible to trigger lazy registration if the version is read
as a zero? This would not introduce any additional atomic instructions
on the fast path.
yes, that is possible. The main problem is the transition from lazy to
non-lazy mode when the first exception is thrown. We must
On 11/22/22 09:25, Richard Biener wrote:
On Tue, Nov 22, 2022 at 9:24 AM Richard Biener
wrote:
On Mon, Nov 21, 2022 at 5:49 PM Jeff Law wrote:
On 11/21/22 09:35, Aldy Hernandez via Gcc-patches wrote:
I've been playing around with removing the legacy VRP code for the
next release.
gcc.target/aarch64/aapcs64/test_dfp_17.c has been failing on
big-endian, because the _Decimal32 on-stack argument is not padded in
the same direction depending on endianness.
This patch fixes the testcase so that it expects the argument in the
right stack location, similarly to what other tests
On Fri, Nov 18, 2022 at 3:47 PM Segher Boessenkool
wrote:
>
> [ Please cc: me and Ke Wen on rs6000 patches ]
>
> On Thu, Nov 17, 2022 at 07:54:29AM +0800, Hongyu Wang wrote:
> > r13-3950-g071e428c24ee8c enables O2 small loop unrolling, but it breaks
> > -fno-unroll-loops for rs6000 with
On Tue, Nov 22, 2022 at 9:43 AM Yixuan Chen wrote:
>
> gcc/testsuite/ChangeLog:
>
> Riscv don't support "-fprefetch-loop-arrays" option, skip.
Looking around other testcases simply add -w to the set of command-line options,
can you do that instead?
OK with that change,
Richard.
> 2022-11-22
The following avoids using type_for_mode on vector modes which might
not work for all frontends. Instead we look for the inner mode
type and use build_vector_type_for_mode instead.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/107672
*
gcc/testsuite/ChangeLog:
Riscv don't support "-fprefetch-loop-arrays" option, skip.
2022-11-22 Yixuan Chen
* gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays"
option, skip.
---
gcc/testsuite/gcc.dg/pr106397.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Mon, Nov 21, 2022 at 06:31:47PM -0500, Jason Merrill via Gcc-patches wrote:
> Tested x86_64-pc-linux-gnu, and also manually changing the HAVE_DECL_STRCHRNUL
> flag. OK for trunk?
>
> -- 8< --
>
> The Contracts implementation uses strchrnul, which is a glibc extension, so
> bootstrap broke on
On Tue, Nov 22, 2022 at 8:59 AM Richard Sandiford via Gcc-patches
wrote:
>
> Wilco Dijkstra writes:
> > Add a reassocation width for FMAs in per-CPU tuning structures. Keep the
> > existing setting for cores with 2 FMA pipes, and use 4 for cores with 4
> > FMA pipes. This improves SPECFP2017 on
On Tue, Nov 22, 2022 at 9:24 AM Richard Biener
wrote:
>
> On Mon, Nov 21, 2022 at 5:49 PM Jeff Law wrote:
> >
> >
> > On 11/21/22 09:35, Aldy Hernandez via Gcc-patches wrote:
> > > I've been playing around with removing the legacy VRP code for the
> > > next release. It's a layered onion to get
On Mon, Nov 21, 2022 at 5:49 PM Jeff Law wrote:
>
>
> On 11/21/22 09:35, Aldy Hernandez via Gcc-patches wrote:
> > I've been playing around with removing the legacy VRP code for the
> > next release. It's a layered onion to get this right, but the first
> > bit is pretty straightforward and may
* Thomas Neumann:
> Hi,
>
> When dynamically linking a fast enough machine hides the latency, but when
> Statically linking or on slower devices this change caused a 5x increase
> in
> Instruction count and 2x increase in cycle count before getting to main.
>
> I have looked at
On Mon, 21 Nov 2022, Qing Zhao wrote:
>
>
> > On Nov 18, 2022, at 11:31 AM, Kees Cook wrote:
> >
> > On Fri, Nov 18, 2022 at 03:19:07PM +, Qing Zhao wrote:
> >> Hi, Richard,
> >>
> >> Honestly, it?s very hard for me to decide what?s the best way to handle
> >> the interaction
> >>
When registering a dynamic unwinding frame the fde list is sorted.
Previously, we split the list into a sorted and an unsorted part,
sorted the later using heap sort, and merged both. That can be
quite slow due to the large number of (expensive) comparisons.
This patch replaces that logic with a
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