Hi!
On Fri, Dec 30, 2022 at 10:22:31AM +0800, Jiufu Guo wrote:
> Considering the limitations of CSE, I try to find other places
> to handle this issue, and notice DSE can optimize below code:
> "[sfp:DI]=x:DI ; y:SI=[sfp:DI]" to "y:SI=x:DI#0".
>
> So, I drafted a patch to update DSE to handle DI-
Hi, Richard:
Could you please help me look at this document? Is there any problem
with my modification?
Thanks!
在 2022/12/27 下午2:42, Lulu Cheng 写道:
Co-authored-by: Yang Yujie
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_classify_address):
Add precessint for
Hi,
Jiufu Guo via Gcc-patches writes:
> Hi,
>
> Jiufu Guo via Gcc-patches writes:
>
>> Hi,
>>
>> Segher Boessenkool writes:
>>
>>> On Fri, Dec 23, 2022 at 08:13:48PM +0100, Richard Biener wrote:
> Am 23.12.2022 um 17:55 schrieb Segher Boessenkool
> :
> There are at least six ve
>Ping. If there are any questions or concerns about the patch, please let me
>know: I'm interested in continuing this cleanup at least for older AMD models.
>
Hi Alexander:
According to the speccpu2017 benchmark result, the patch looks good in
lujiazui.
BR
Mayshao
>I noticed I had an ext
On 12/29/22 07:50, Philipp Tomsich wrote:
We have two issues around min/max here:
1. That it doesn't apply to the SImode abs case (which is due to
expand_abs_nojump() blindly testing for the current mode in smax_optab).
Mode testing is inherent in the optab query interface.
2. That we h
gcc/
* config/xtensa/xtensa.cc (xtensa_return_in_memory): Use
GP_RETURN_* instead of magic constant.
---
gcc/config/xtensa/xtensa.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index e726a115029f..ae4
On Thu, Dec 29, 2022 at 4:33 AM Takayuki 'January June' Suwa
wrote:
>
> Parhaps no problem, but for safety.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_expand_prologue): Fix to check
> DF availability before use of DF_* macros.
> ---
> gcc/config/xtensa/xtensa.cc | 2
From: Ju-Zhe Zhong
Currently we use pred_mov to to do the codegen for vse intrinsics. However, it
generates inferior codegen when I am testing AVL model of VSETVL PASS using vse
intrinsics.
Consider this following code:
void f2 (int * restrict in, int * restrict out, void * restrict mask_in, in
On Wed, 28 Dec 2022 at 19:18, Raphael Moreira Zinsly <
rzin...@ventanamicro.com> wrote:
> The Zbb min/max pattern was not matching 32-bit sources when
> compiling for 64-bit.
> This patch separates the pattern into SImode and DImode, and
> use a define_expand to handle SImode on 64-bit.
> zbb-min-
On 12/29/22 05:23, Raphael Zinsly wrote:
On Wed, Dec 28, 2022 at 10:36 PM Jeff Law wrote:
On 12/28/22 11:18, Raphael Moreira Zinsly wrote:
The Zbb min/max pattern was not matching 32-bit sources when
compiling for 64-bit.
This patch separates the pattern into SImode and DImode, and
use a
Parhaps no problem, but for safety.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_expand_prologue): Fix to check
DF availability before use of DF_* macros.
---
gcc/config/xtensa/xtensa.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xte
On Wed, Dec 28, 2022 at 10:36 PM Jeff Law wrote:
>
>
>
> On 12/28/22 11:18, Raphael Moreira Zinsly wrote:
> > The Zbb min/max pattern was not matching 32-bit sources when
> > compiling for 64-bit.
> > This patch separates the pattern into SImode and DImode, and
> > use a define_expand to handle SI
Iain Sandoe writes:
> Hi Gaius,
>
> I’m finding it hard to figure out how the configuration is supposed to work
> for cross compilers (and more so for Canadian/native crosses).
>
> Apologies if this is already answered in other review (but maybe some notes
> would help in that case).
>
> questi
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