Re: [x86_64 PATCH] More TImode parameter passing improvements.

On Wed, Jul 19, 2023 at 10:07 PM Roger Sayle wrote: > > > This patch is the next piece of a solution to the x86_64 ABI issues in > PR 88873. This splits the *concat3_3 define_insn_and_split > into two patterns, a TARGET_64BIT *concatditi3_3 and a !TARGET_64BIT > *concatsidi3_3. This allows us to

Re: [GCC 13 PATCH] aarch64: Remove architecture dependencies from intrinsics

Andrew Carlotti writes: > Updated patch to fix the fp16 intrinsic pragmas, and pushed to master. > OK to backport to GCC 13? OK, thanks. Richard > Many intrinsics currently depend on both an architecture version and a > feature, despite the corresponding instructions being available within > GC

Re: [PATCH v4] RISC-V: Support CALL for RVV floating-point dynamic rounding

LGTM from my side but plz wait for comments from other reviewers. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-07-20 14:43 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang Subject: [PATCH v4] RISC-V: Support CALL for RVV floating-point dynamic rounding From: Pan Li In ba

RE: [PATCH v1] RISC-V: Align the pattern format in vector.md

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Thursday, July 20, 2023 2:40 PM To: Li, Pan2 ; gcc-patches Cc: jeffreyalaw ; Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Align the pattern format in vector.md LGTM. Thanks for fixing formats. You can go

[PATCH v4] RISC-V: Support CALL for RVV floating-point dynamic rounding

From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value

Re: [PATCH v1] RISC-V: Align the pattern format in vector.md

LGTM. Thanks for fixing formats. You can go ahead commit it. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-07-20 14:32 To: gcc-patches CC: juzhe.zhong; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Align the pattern format in vector.md From: Pan Li There are so

[PATCH v1] RISC-V: Align the pattern format in vector.md

From: Pan Li There are some format-unaligned pattern in vector.md, this patch would like to align the format for these patterns. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector.md: Align pattern format. --- gcc/config/riscv/vector.md | 850 +

Re: Re: [PATCH] VECT: Support floating-point in-order reduction for length loop control

Yes. We want to be consistent. I am planning to change all previous "LEN_MASK_*" into "MASK_LEN_*" juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-07-20 14:22 To: juzhe.zhong; gcc-patches CC: rdapp.gcc; richard.sandiford; rguenther Subject: Re: [PATCH] VECT: Support floating-point in-order r

Re: [PATCH] VECT: Support floating-point in-order reduction for length loop control

Hi Juzhe, I just noticed that we recently started calling things MASK_LEN (instead of LEN_MASK before) with the reductions. Wouldn't we want to be consistent here? Especially as the length takes precedence. I realize the preparational work like optabs is already upstream but still wanted to brin

Re: [PATCH v3] Implement new RTL optimizations pass: fold-mem-offsets.

On 7/18/23 21:31, Jeff Law via Gcc-patches wrote: In a run with -fno-fold-mem-offsets, the same insn 93 is successfully grok'ed by cprop_hardreg, | (insn 93 337 522 11 (set (mem/c:DF (plus:DI (reg/f:DI 2 sp) |    (const_int 8 [0x8])) [4 %sfp+-8 S8 A64]) |    (const_double:D

[PATCH] VECT: Support floating-point in-order reduction for length loop control

From: Ju-Zhe Zhong Hi, Richard and Richi. This patch support floating-point in-order reduction for loop length control. Consider this following case: float foo (float *__restrict a, int n) { float result = 1.0; for (int i = 0; i < n; i++) result += a[i]; return result; } When compile

Re: [PATCH]AArch64 fix regexp for live_1.c sve test

Tamar Christina writes: > Hi All, > > The resulting predicate register of a whilelo is not > restricted to the lower half of the predicate register file. > > As such these tests started failing after recent changes > because the whilelo outside the loop is getting assigned p15. It's the whilelo i

[PATCH] Fix fp16 related testcase failure for i686.

> I see some regressions most likely with this change on i686-linux, > in particular: > +FAIL: gcc.dg/pr107547.c (test for excess errors) > +FAIL: gcc.dg/torture/floatn-convert.c -O0 (test for excess errors) > +UNRESOLVED: gcc.dg/torture/floatn-convert.c -O0 compilation failed to > produce execu

[PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. When the user specifies PTImode as an attribute, it breaks. Created a tree node to handle PTImode types. PTImode attribute helps in generating even/odd register pairs on 128 bits. 2023-07-20 Jeevitha Palanisam

Re: [PATCH v3] RISC-V: Support CALL for RVV floating-point dynamic rounding

Thanks. Some more tests: test 1: if (){ vadd (integer RVV intrinsic) }else{ CALL } vfadd static return test 2: if (){ vfadd DYN }else{ CALL } vfadd static return test 3: if (){ vfadd static }else{ CALL } vfadd static return I think that's enough, no more tests. juzhe.zh...@riv

RE: [PATCH v2] RISC-V: Support CALL for RVV floating-point dynamic rounding

Sure thing, update the PATCH v3 with below 4+4+16 tests, as well as rvv/riscv.exp passed. https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624988.html Pan From: juzhe.zh...@rivai.ai Sent: Wednesday, July 19, 2023 2:38 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.chen

[committed] testsuite: Fix C++ UDL tests failing on 32-bit arch [PR103902]

These tests need to use "size_t" rather than "unsigned long" for the user-defined literal function arguments. gcc/testsuite/ChangeLog: PR preprocessor/103902 * g++.dg/cpp0x/udlit-extended-id-1.C: Change "unsigned long" to "size_t" throughout. * g++.dg/cpp0x/udlit-e

[PATCH v3] RISC-V: Support CALL for RVV floating-point dynamic rounding

From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value

[PATCH] Correct Granite Rapids{, D} documentation

Hi all, This patch will fix the documentation error in invoke.texi where includes AVX512VP2INTERSECT in GNR and GNR-D previously. Commit ad obvious change and backport to GCC 13 branch. Thx, Haochen gcc/Changelog: * doc/invoke.texi: Remove AVX512VP2INTERSECT in Granite Rapids{,

RE: [PATCH V3] RISC-V: Refactor RVV machine modes

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, July 20, 2023 10:16 AM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng ; Robin Dapp ; Jeff Law Subject: Re: [PATCH V3] RISC-V: Refactor RVV machine modes LGTM, I mus

[PATCH] Move combine over to statistics_counter_event.

Since we have statistics_counter_event now, combine should use that instead of it is own custom printing of statistics. The only thing that is not done any more after this patch is printing out the total stats for the whole TU. Note you need to use -fdump-rtl-combine-stats to get the stats in the

Re: [PATCH] c++: passing partially inst tmpl as ttp [PR110566]

On 7/19/23 14:05, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/13? -- >8 -- Since the arguments 'pargs' passed to the coerce_template_parms from coerce_template_template_parms are always a full set, we need to make sure we always pass the p

Re: [PATCH V3] RISC-V: Refactor RVV machine modes

LGTM, I must say the number of modifications is less than my expect :) And it's a really big move for RVV implementation! Juzhe-Zhong 於 2023年7月20日 週四 07:22 寫道： > Current machine modes layout is hard to maintain && read && understand. > > For a LMUL = 1 SI vector mode: > 1. VNx1SI mode when TA

Re: [PATCH v5 4/5] c++modules: report imported CMI files as dependencies

On Wed, Jul 19, 2023 at 17:11:08 -0400, Nathan Sidwell wrote: > GCC is neither of these descriptions. a CMI does not contain the transitive > closure of its imports. It contains an import table. That table lists the > transitive closure of its imports (it needs that closure to do remapping),

Re: [GCC 13 PATCH] aarch64: Remove architecture dependencies from intrinsics

On Wed, Jul 19, 2023 at 07:35:26PM +0100, Ramana Radhakrishnan wrote: > On Wed, Jul 19, 2023 at 5:44 PM Andrew Carlotti via Gcc-patches > wrote: > > > > Updated patch to fix the fp16 intrinsic pragmas, and pushed to master. > > OK to backport to GCC 13? > > > > > > Many intrinsics currently depend

Re: Re: [PATCH V2] RISC-V: Refactor RVV machine modes

Yes. It reduces 3.4K from 17.5K to 14.1k. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-07-20 07:15 To: Juzhe-Zhong; gcc-patches CC: kito.cheng; kito.cheng; rdapp.gcc Subject: Re: [PATCH V2] RISC-V: Refactor RVV machine modes On 7/19/23 16:45, Juzhe-Zhong wrote: > Current machine modes la

Re: [PATCH V2] RISC-V: Refactor RVV machine modes

On 7/19/23 16:45, Juzhe-Zhong wrote: Current machine modes layout is hard to maintain && read && understand. For a LMUL = 1 SI vector mode: 1. VNx1SI mode when TARGET_MIN_VLEN = 32. 2. VNx2SI mode when TARGET_MIN_VLEN = 64. 3. VNx4SI mode when TARGET_MIN_VLEN = 128. Such implementat

[PATCH v4] Introduce attribute sym

On Jul 18, 2023, Richard Biener wrote: > I think the __symver__ attribute does something similar already so > maybe use __attribute__((__sym__("foo")))? Cool, thanks, that will do. Regstrapped on x86_64-linux-gnu. Ok to install? This patch introduces an attribute to add extra asm names (alia

[committed] libstdc++: Do not define inaccurate from_chars for _Float128 [PR110077]

Tested x86_64-linux and sparc-solaris. Pushed to trunk. -- >8 -- I think r14-1431-g7037e7b6e4ac41 was wrong to try to define the _Float128 overload unconditionally. Not all targets need it, so defining the lossy fallback using long double is not useful (and caused an ABI change on Solaris x86).

[committed] libstdc++: Check for std::ratio in arithmetic and comparisons [PR110593]

Tested x86_64-linux. Pushed to trunk. -- >8 -- The standard says that it should be ill-formed to use std::ratio_equal etc. with types which are not specializations of std::ratio. This implements that requirement. We don't need to add assertions to every one of the class templates, because many o

[PATCH] PR c/110699: Defend against error_mark_node in gimplify.cc.

This patch resolves PR c/110699, an ICE-after-error regression, by adding a check that the array type isn't error_mark_node in gimplify_compound_lval. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no n

[pushed] analyzer: fix ICE on division of tainted floating-point values [PR110700]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-2658-gb86c0fe327a519. gcc/analyzer/ChangeLog: PR analyzer/110700 * region-model-manager.cc (region_model_manager::get_or_create_int_cst): Assert that we have an integral or pointer

Re: [PATCH] c++: Improve printing of base classes [PR110745]

On 7/19/23 17:51, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? OK, thanks. -- >8 -- This patch changes warning: missing initializer for member 'D::' [-Wmissing-field-initializers] to warning: missing initializer for member 'D::B' [-Wmissing-fiel

[PATCH] c++: Improve printing of base classes [PR110745]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- This patch changes warning: missing initializer for member 'D::' [-Wmissing-field-initializers] to warning: missing initializer for member 'D::B' [-Wmissing-field-initializers] PR c++/110745 gcc/cp/ChangeLog:

[PING 2] [PATCH] Less warnings for parameters declared as arrays [PR98541, PR98536]

Ok for gcc-14 now? Am Dienstag, dem 04.04.2023 um 19:31 -0600 schrieb Jeff Law: > > > On 4/3/23 13:34, Martin Uecker via Gcc-patches wrote: > > > > > > With the relatively new warnings (11..) affecting VLA bounds, > > I now get a lot of false positives with -Wall. In general, I find > > th

Re: [PATCH v5 4/5] c++modules: report imported CMI files as dependencies

On 7/18/23 20:01, Ben Boeckel wrote: On Tue, Jul 18, 2023 at 16:52:44 -0400, Jason Merrill wrote: On 6/25/23 12:36, Ben Boeckel wrote: On Fri, Jun 23, 2023 at 08:12:41 -0400, Nathan Sidwell wrote: On 6/22/23 22:45, Ben Boeckel wrote: On Thu, Jun 22, 2023 at 17:21:42 -0400, Jason Merrill wrote

[PATCH] libstdc++: Fix preprocessor conditions for std::from_chars [PR109921]

I'm testing this patch for gcc-13 as a better fix for PR109921, without the breakage that r14-1431-g7037e7b6e4ac41 caused on trunk. If testing goes well I'll push this before the 13.2 release candidate. -- >8 -- We use the from_chars_strtod function with __strtof128 to read a _Float128 value, bu

[x86_64 PATCH] More TImode parameter passing improvements.

This patch is the next piece of a solution to the x86_64 ABI issues in PR 88873. This splits the *concat3_3 define_insn_and_split into two patterns, a TARGET_64BIT *concatditi3_3 and a !TARGET_64BIT *concatsidi3_3. This allows us to add an additional alternative to the the 64-bit version, enabli

Re: [PATCH] c++: -Wmissing-field-initializers and empty class [PR110064]

On Wed, Jul 19, 2023 at 03:36:49PM -0400, Jason Merrill wrote: > On 7/19/23 15:20, Marek Polacek wrote: > > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > > OK. We might also improve the diagnostic for base classes, perhaps by > teaching dump_simple_decl about DECL_FIELD_IS_BASE?

Re: [PATCH] c++: -Wmissing-field-initializers and empty class [PR110064]

On 7/19/23 15:20, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? OK. We might also improve the diagnostic for base classes, perhaps by teaching dump_simple_decl about DECL_FIELD_IS_BASE? -- >8 -- Let's suppress -Wmissing-field-initializers for empty clas

[PATCH v2] libstdc++: Define _GLIBCXX_HAS_BUILTIN_TRAIT

This patch defines _GLIBCXX_HAS_BUILTIN_TRAIT macro, which will be used as a flag to toggle the use of built-in traits in the type_traits header through _GLIBCXX_NO_BUILTIN_TRAITS macro, without needing to modify the source code. libstdc++-v3/ChangeLog: * include/bits/c++config (_GLIBCXX_

Re: [PATCH] libstdc++: Define _GLIBCXX_HAS_BUILTIN_TRAIT

On Wed, Jul 19, 2023 at 11:48 AM Patrick Palka wrote: > > On Tue, 18 Jul 2023, Ken Matsui via Libstdc++ wrote: > > > This patch defines _GLIBCXX_HAS_BUILTIN_TRAIT, which will be used as a > > flag to toggle built-in traits in the type_traits header. Through this > > macro function and _GLIBCXX_NO_

Re: [PATCH] c++: fix ICE with designated initializer [PR110114]

On 7/19/23 14:38, Marek Polacek wrote: On Wed, Jul 19, 2023 at 02:32:15PM -0400, Patrick Palka wrote: On Wed, 19 Jul 2023, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? LGTM. It might be preferable to check COMPLETE_TYPE_P in the caller instead, so that w

Re: [PATCH] testsuite: fix allocator-opt1.C FAIL with old ABI

Ping. On Mon, Jul 10, 2023 at 04:33:26PM -0400, Marek Polacek via Gcc-patches wrote: > Running > $ make check-g++ > RUNTESTFLAGS='--target_board=unix\{-D_GLIBCXX_USE_CXX11_ABI=0,\} > dg.exp=allocator-opt1.C' > yields: > > FAIL: g++.dg/tree-ssa/allocator-opt1.C -std=c++98 scan-tree-dump-times

[PATCH] c++: -Wmissing-field-initializers and empty class [PR110064]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- Let's suppress -Wmissing-field-initializers for empty classes. Here I don't think I need the usual COMPLETE_TYPE_P/dependent_type_p checks. PR c++/110064 gcc/cp/ChangeLog: * typeck2.cc (process_init_construc

[PATCH] Use strtol instead of std::stoi in gensupport.cc

Tested on trunk with hppa64-hp-hpux11.11. Okay? Dave --- Use strtol instead of std::stoi [PR110646] Implementation of std::stoi was overlooked on hppa-hpux, so use strtol instead. 2023-07-19 John David Anglin gcc/ChangeLog: PR bootstrap/110646 * gensupport.cc(class conlist

Re: [V1][PATCH 0/3] New attribute "element_count" to annotate bounds for C99 FAM(PR108896)

>> >> The point is: allocation size should synced with the value of “counted_by”. >> LLVM’s RFC also have the similar requirement: >> https://discourse.llvm.org/t/rfc-enforcing-bounds-safety-in-c-fbounds-safety/70854#maintaining-correctness-of-bounds-annotations-18 > > Right, I'm saying it woul

Re: [PATCH] libstdc++: Define _GLIBCXX_HAS_BUILTIN_TRAIT

On Tue, 18 Jul 2023, Ken Matsui via Libstdc++ wrote: > This patch defines _GLIBCXX_HAS_BUILTIN_TRAIT, which will be used as a > flag to toggle built-in traits in the type_traits header. Through this > macro function and _GLIBCXX_NO_BUILTIN_TRAITS macro, we can switch the > use of built-in traits w

Re: [PATCH] c++: fix ICE with designated initializer [PR110114]

On Wed, Jul 19, 2023 at 02:32:15PM -0400, Patrick Palka wrote: > On Wed, 19 Jul 2023, Marek Polacek wrote: > > > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > > LGTM. It might be preferable to check COMPLETE_TYPE_P in the caller > instead, so that we avoid inspecting CLASSTYPE_N

Re: [GCC 13 PATCH] aarch64: Remove architecture dependencies from intrinsics

On Wed, Jul 19, 2023 at 5:44 PM Andrew Carlotti via Gcc-patches wrote: > > Updated patch to fix the fp16 intrinsic pragmas, and pushed to master. > OK to backport to GCC 13? > > > Many intrinsics currently depend on both an architecture version and a > feature, despite the corresponding instructio

Re: [PATCH] c++: fix ICE with designated initializer [PR110114]

On Wed, 19 Jul 2023, Marek Polacek wrote: > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? LGTM. It might be preferable to check COMPLETE_TYPE_P in the caller instead, so that we avoid inspecting CLASSTYPE_NON_AGGREGATE on an incomplete class type, and so that the caller doesn't "c

Re: [PATCH] c++: passing partially inst tmpl as ttp [PR110566]

On Wed, Jul 19, 2023 at 2:05 PM Patrick Palka wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > trunk/13? > > -- >8 -- > > Since the arguments 'pargs' passed to the coerce_template_parms from > coerce_template_template_parms are always a full set, we need to mak

[PATCH] c++: passing partially inst tmpl as ttp [PR110566]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/13? -- >8 -- Since the arguments 'pargs' passed to the coerce_template_parms from coerce_template_template_parms are always a full set, we need to make sure we always pass the parameters of the most general template be

[PATCH] c++: fix ICE with designated initializer [PR110114]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- r13-1227 added an assert checking that the index in a CONSTRUCTOR is a FIELD_DECL. That's a reasonable assumption but in this case we never called reshape_init due to the type being incomplete, and so the index remained an ide

[pushed][LRA]: Check and update frame to stack pointer elimination after stack slot allocation

The following patch is necessary for porting avr to LRA. The patch was successfully bootstrapped and tested on x86-64, aarch64, and ppc64le. There is still avr poring problem with reloading of subreg of frame pointer.  I'll address it later on this week. commit 2971ff7b1d564ac04b537d907c70e

Re: [PATCH 0/8] Tweak predicate macros in tree

On Wed, Jul 19, 2023 at 12:08 AM Richard Biener wrote: > > On Wed, Jul 19, 2023 at 1:34 AM Ken Matsui via Gcc-patches > wrote: > > > > This patch series tweaks predicate macros in tree.h to make the code more > > readable. TYPE_REF_P is moved to tree.h and used for INDIRECT_TYPE_P and > > TYPE_RE

[PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. There are no instructions that do traditional AltiVec addresses (i.e. with the low four bits of the address masked off) for OOmode and XOmode objects. The solution is to modify the constraints used in the movoo

[GCC 13 PATCH] aarch64: Remove architecture dependencies from intrinsics

Updated patch to fix the fp16 intrinsic pragmas, and pushed to master. OK to backport to GCC 13? Many intrinsics currently depend on both an architecture version and a feature, despite the corresponding instructions being available within GCC at lower architecture versions. LLVM has already remo

Re: [V1][PATCH 0/3] New attribute "element_count" to annotate bounds for C99 FAM(PR108896)

More thoughts on the following example Kees provided: > On Jul 17, 2023, at 7:40 PM, Kees Cook wrote: >> >> The counted_by attribute is used to annotate a Flexible array member on how >> many elements it will have. >> However, if this information can not accurately reflect the real number of

[committed] libstdc++: Fix formatting of negative chrono::hh_mm_ss

Tested x86_64-linux. Pushed to trunk. -- >8 -- When formatting with an empty chrono spec ("{}") two minus signs were being added to hh_mm_ss values. This is because the __is_neg flag was checked to add one explicitly, and then the ostream operator added another one. We should only check the __is

[committed] libstdc++: Fix locale-specific duration formatting [PR110719]

Tested x86_64-linux. Pushed to trunk. -- >8 -- The r14-2640-gf4bce119f617dc commit only removed fractional seconds for time points, but it needs to be done for durations and hh_mm_ss types too. libstdc++-v3/ChangeLog: PR libstdc++/110719 * include/bits/chrono_io.h (__formatter_c

Re: [PATCH] core: Support heap-based trampolines

Am Mittwoch, dem 19.07.2023 um 15:23 +0100 schrieb Iain Sandoe: > Hi Martin, > > > On 19 Jul 2023, at 11:43, Martin Uecker via Gcc-patches > > wrote: > > > > Am Mittwoch, dem 19.07.2023 um 10:29 +0100 schrieb Iain Sandoe: > > > > > On 19 Jul 2023, at 10:04, Martin Uecker > > > > wrote: > > >

[PATCH 2/2][frontend]: Add novector C pragma

Hi All, FORTRAN currently has a pragma NOVECTOR for indicating that vectorization should not be applied to a particular loop. ICC/ICX also has such a pragma for C and C++ called #pragma novector. As part of this patch series I need a way to easily turn off vectorization of particular loops, part

[PATCH 1/2][frontend] Add novector C++ pragma

Hi All, FORTRAN currently has a pragma NOVECTOR for indicating that vectorization should not be applied to a particular loop. ICC/ICX also has such a pragma for C and C++ called #pragma novector. As part of this patch series I need a way to easily turn off vectorization of particular loops, part

Re: [PATCH] Add __builtin_iseqsig()

6 weeks later, I’d like to ask a global maintainer to review this. The idea was okay’ed previously by Joseph Myers, but he asked for testing of both the quiet and signalling NaN cases, which is now done. FX > Le 6 juin 2023 à 20:15, FX Coudert a écrit : > > Hi, > > (It took me a while to get

Re: [PATCH 2/3] testsuite: Require 128-bit vectors for bb-slp-pr95839.c

On Wed, 12 Jul 2023, Richard Biener wrote: > > > That said, we should handle this better so can you file an > > > enhancement bugreport for this? > > > > Filed as PR -optimization/110630. > > Thanks! Thanks for making this improvement. I've checked MIPS results and code produced now is as fo

Re: [PATCH] RISC-V: Refactor RVV machine modes

Thansk, that's really awesome! One comment about mode iterator is the naming seems like still prefixed with VNX which inconsistent with new mode naming scheme. > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index cd5b19457f8..03e19259505 100644 > --- a/gcc/config/riscv

Re: [PATCH] core: Support heap-based trampolines

Hi Martin, > On 19 Jul 2023, at 11:43, Martin Uecker via Gcc-patches > wrote: > > Am Mittwoch, dem 19.07.2023 um 10:29 +0100 schrieb Iain Sandoe: >>> On 19 Jul 2023, at 10:04, Martin Uecker >>> wrote: >> > On 17 Jul 2023, >>> >> You mention setjmp/longjmp - on darwin and othe

Re: [PATCH v3] Implement new RTL optimizations pass: fold-mem-offsets.

On 7/19/23 02:08, Manolis Tsamis wrote: de. I stumbled upon the same thing when doing an aarch64 bootstrap build yesterday. Given that this causes issues, maybe doing int icode = INSN_CODE (insn); ... INSN_CODE (insn) = icode; Is a good option and should also be more performant. I

Re: [PATCH] c++: fix ICE with is_really_empty_class [PR110106]

On Tue, 18 Jul 2023, Marek Polacek via Gcc-patches wrote: > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk and branches? Looks reasonable to me. Though I wonder if we could also fix this by not checking potentiality at all in this case? The problematic call to is_rvalue_constant_ex

Re: [PATCH] middle-end/61747 - conditional move expansion and constants

On Wed, Jul 19, 2023 at 01:36:23PM +, Richard Biener wrote: > > If we have a match between at least one of the comparison operands and > > op2/op3, I think having equivalency there is perhaps more important than > > the canonicalization, but it would be nice not to break it even if there > > is

RE: [PATCH] VECT: Add mask_len_fold_left_plus for in-order floating-point reduction

Committed as passed both the bootstrap and regression test, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, July 19, 2023 4:17 PM To: Ju-Zhe Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [

Re: [PATCH] middle-end/61747 - conditional move expansion and constants

On Wed, 19 Jul 2023, Jakub Jelinek wrote: > On Tue, Jul 18, 2023 at 01:25:45PM +0200, Richard Biener wrote: > > > > PR middle-end/61747 > > * internal-fn.cc (expand_vec_cond_optab_fn): When the > > value operands are equal to the original comparison operands > > preserve that equa

Re: [PATCH] match.pd: Implement missed optimization (~X | Y) ^ X -> ~(X & Y) [PR109986]

Trying to lower converts to operands through, for example, (for op (bit_ior bit_and bit_xor) (for rop (bit_xor bit_ior bit_and) (simplify (op:c (nop_convert (rop @0 @1)) @3) (op (rop (convert:type @0) (convert:type @1)) @3 (simplify (convert (bit_not @0)) (bit_not (convert:type @0))

Re: [PATCH] middle-end/61747 - conditional move expansion and constants

On Tue, Jul 18, 2023 at 01:25:45PM +0200, Richard Biener wrote: > > PR middle-end/61747 > * internal-fn.cc (expand_vec_cond_optab_fn): When the > value operands are equal to the original comparison operands > preserve that equality by re-using the comparison expansion. >

[OG13][committed] libgomp.fortran/map-subarray-5.f90: Fix for shared-mem device/host

Fix testcase if from "OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic" which has been semi-submitted* to mainline as: "[PATCH 09/14] OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic" https://gcc.gnu.org/pipermail/gcc-patches/2023-June/6222

Re: [GCC 13 PATCH] PR target/109973: CCZmode and CCCmode variants of [v]ptest.

On Wed, Jul 19, 2023 at 2:21 PM Richard Biener wrote: > > On Sun, Jun 11, 2023 at 12:55 AM Roger Sayle > wrote: > > > > > > This is a backport of the fixes for PR target/109973 and PR target/110083. > > > > This backport to the releases/gcc-13 branch has been tested on > > x86_64-pc-linux-gnu wi

[OG13][committed] gfortran.dg/gomp/affinity-clause-1.f90: Fix scan-tree-dump

OG13 (devel/omp/gcc-13) has a patch which uses sometimes the tree's array representation. The patch unfortunately did not make it to mainline so far. The here attached/committed patch adapts the expected dump for the OG13 variant to unfail this testcase. With this commit, gfortran/gomp/ has no fa

Re: [PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible

On 7/19/23 04:25, Richard Biener wrote: On Wed, 19 Jul 2023, YunQiang Su wrote: Eric Botcazou ?2023?7?19??? 17:45??? I don't see that. That's definitely not what GCC expects here, the left-most word of the doubleword should be unchanged. Your testcase should be a dg-do-run and probably

Re: [GCC 13 PATCH] PR target/109973: CCZmode and CCCmode variants of [v]ptest.

On Sun, Jun 11, 2023 at 12:55 AM Roger Sayle wrote: > > > This is a backport of the fixes for PR target/109973 and PR target/110083. > > This backport to the releases/gcc-13 branch has been tested on > x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and > without --target_boar

[committed] tree-switch-conversion: Fix a comment typo

Hi! I've noticed a comment typo, this patch fixes that. Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk as obvious. 2023-07-19 Jakub Jelinek * tree-switch-conversion.h (class bit_test_cluster): Fix comment typo. --- gcc/tree-switch-conversion.h.jj 2023-

Re: vectorizer: Avoid an OOB access from vectorization

On Tue, 18 Jul 2023, Matthew Malcomson wrote: > Tamar pointed out it would be good to have a `scan-tree-dump` in the testcase > just to make sure that when something is currently vectorizing it stays > vectorizing (and hence that the new code is still likely running). > > Attached patch has that

[committed] libstdc++: Avoid warning in std::format

Tested x86_64-linux. Pushed to trunk. -- >8 -- With -Wmaybe-uninitialized -Wsystem-headers there's a warning about creating a string_view from an uninitalized array. Initializing the first element of the array avoids the warning. libstdc++-v3/ChangeLog: * include/std/format (__write_pad

[committed] libstdc++: Implement correct locale-specific chrono formatting [PR110719]

Tested x86_64-linux. Pushed to trunk. I'll backport it to gcc-13 some time after the 13.2 release. -- >8 -- This fixes some TODOs in the C++20 format support, where the locale-specific output was incorrect or unimplemented. The approach taken here is to either use the formatting locale's std::t

Re: [PATCH] wide-int: Fix up wi::divmod_internal [PR110731]

On Wed, 19 Jul 2023, Jakub Jelinek wrote: > Hi! > > As the following testcase shows, wi::divmod_internal doesn't handle > correctly signed division with precision > 64 when the dividend (and likely > divisor as well) is the type's minimum and the precision isn't divisible > by 64. > > A few line

[PATCH] wide-int: Fix up wi::divmod_internal [PR110731]

Hi! As the following testcase shows, wi::divmod_internal doesn't handle correctly signed division with precision > 64 when the dividend (and likely divisor as well) is the type's minimum and the precision isn't divisible by 64. A few lines above what the patch hunk changes is: /* Make the divis

[committed] testsuite: Add 64-bit vector variant for bb-slp-pr95839.c

Add dual-single float vector test complementing bb-slp-pr95839.c. gcc/testsuite/ * gcc.dg/vect/bb-slp-pr95839-v8.c: New test. --- Committed with Richard Biener's approval: . --- gcc/testsuite/gcc.dg/vect/bb-slp-pr95

Re: [PATCH] Implement Bit-field lowering

On Fri, Jul 14, 2023 at 7:49 AM naveenh--- via Gcc-patches wrote: > > From: Naveen H S > > This patch adds lowering bit-field and opposite endian accesses pass. > The patch addresses many issues in:- > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=19466 A little bit more description would be nice

Re: [PATCH 1/2] [i386] Support type _Float16/__bf16 independent of SSE2.

On Wed, Jul 19, 2023 at 01:58:21PM +0800, Hongtao Liu wrote: > > LGTM, if you need someone to rubber-stamp the patch. I'm not really > > versed in this part of the compiler, so please wait a day if someone > > has anything to say about the patch. > Thanks, pushed to trunk. I see some regressions m

Re: [committed] - Re: [patch] OpenMP/Fortran: Non-rectangular loops with constant steps other than 1 or -1 [PR107424]

Hi Tobias! On 2023-07-19T10:26:12+0200, Tobias Burnus wrote: > Now committed as Rev. r14-2634-g85da0b40538fb0 On devel/omp/gcc-13 branch, the corresponding commit b003e6511754dce475f7f5b0c5cd887a177e41b3 "OpenMP/Fortran: Non-rectangular loops with constant steps other than 1 or -1 [PR107424]" i

Re: [PATCH] core: Support heap-based trampolines

Am Mittwoch, dem 19.07.2023 um 10:29 +0100 schrieb Iain Sandoe: > Hi Martin, > > > On 19 Jul 2023, at 10:04, Martin Uecker > > wrote: > > > > > On 17 Jul 2023, > > > > > > > > > > You mention setjmp/longjmp - on darwin and other platforms > > > requiring > > > > > non-stack based trampolines

Re: [PATCH 3/3] testsuite: Require vectors of doubles for pr97428.c

On Wed, 12 Jul 2023, Richard Biener wrote: > > Applied, thanks. OK to backport to the active branches? > > Yes. Now backported, thanks. Maciej

Re: [PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible

On Wed, 19 Jul 2023, YunQiang Su wrote: > Eric Botcazou ?2023?7?19??? 17:45??? > > > > > I don't see that. That's definitely not what GCC expects here, > > > the left-most word of the doubleword should be unchanged. > > > > > > Your testcase should be a dg-do-run and probably more like > > > > >

[committed] libstdc++: Check for multiple modifiers in chrono format string [PR110708]

Tested x86_64-linux. Pushed to trunk. This should be backported to gcc-13 too, but it can wait until 13.3 (it's just an accepts-invalid and unlikely to affect anybody in practice). -- >8 -- The logic for handling modified chrono specs like %Ey was just restarting the loop after each modifier, an

Re: [PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible

Eric Botcazou 于2023年7月19日周三 17:45写道： > > > I don't see that. That's definitely not what GCC expects here, > > the left-most word of the doubleword should be unchanged. > > > > Your testcase should be a dg-do-run and probably more like > > > > NOMIPS16 int __attribute__((noipa)) test (const unsign

[PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

This patch completes the recognition of Zicond when the select pattern with condition eq or neq to 0 (using equality as an example), namely: 1 rd = (rs2 == 0) ? non-imm : 0 2 rd = (rs2 == 0) ? non-imm : non-imm 3 rd = (rs2 == 0) ? reg : non-imm 4 rd = (rs2 == 0) ? reg : reg gcc/ChangeLog:

[PATCH 1/5] [RISC-V] Recognize Zicond extension

This patch is the minimal support for Zicond extension, include the extension name, mask and target defination. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * config/riscv/riscv-opts.h (MASK_ZICOND): New mask. (TARGET_ZICOND): New target. gcc/tests

[PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution

This patch completes the recognition of conditional execution (using equality as an example), namely: 1 rd = (rc == 0) ? (rs1 arith_op rs2) : rs1 Here, arith_op represents the arithmetic operation symbol, which has 8 possibilities: + - | ^ << >>(Shift Right Arithmetic) >>(Shift Right Logical) &

[PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero

This patch completes the recognition of Zicond when the select pattern with condition eq or neq to non-zero (using equality as an example), namely: 1 rd = (rs2 == non-imm) ? 0 : rs1 2 rd = (rs2 == reg) ? 0 : rs1 At the same time, more Zicond non basic semantic test cases have been added. gcc/Cha

[PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics

This patch completes the recognition of the basic semantics defined in the spec, namely: Conditional zero, if condition is equal to zero rd = (rs2 == 0) ? 0 : rs1 Conditional zero, if condition is non zero rd = (rs2 != 0) ? 0 : rs1 gcc/ChangeLog: * config/riscv/riscv.md: Include zico

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