Hi Andre,
I apologise for the slow response. It's been something of a heavy week...
This is good for mainline.
Thanks
Paul
PS That's good news about the funding. Maybe we will get to see "built in"
coarrays soon?
On Tue, 4 Jun 2024 at 11:25, Andre Vehreschild wrote:
> Hi all,
>
> attached
On Thu, Jun 6, 2024 at 6:07 PM Roger Sayle wrote:
>
>
> Hi Hongtao,
> Here's the third revision of my improved ternlog handling patch for x86.
> This addresses the previously discovered problems, adding a check for
> memory_operand, and adds four new test cases, to confirm that the
> appropriate f
This patch is to optimize the runtime execution of gcd. Mathematically,
it computes with the same algorithm as before, but subtractions and
branches are rearranged to encourage generation of code that can use
flags from the subtractions for conditional moves. Additionally, most
pairs of integers ar
On May 28, 2024, Jason Merrill wrote:
> On 5/25/24 08:12, Alexandre Oliva wrote:
>> On Apr 27, 2023, Alexandre Oliva wrote:
>>> On Apr 14, 2023, Alexandre Oliva wrote:
On Mar 23, 2023, Alexandre Oliva wrote:
> This patch introduces infrastructure for targets to add an offset to
>
Hi Gerald,
Gerald Pfeifer wrote:
+++ b/htdocs/gcc-15/changes.html
+
+ https://gcc.gnu.org/projects/gomp/";>OpenMP
Can you please make this a relative link, i.e. "../projects/gomp/"?
Good point. I thought such links should be absolute because of
(www.)GNU.org, i.e.
https://www.gnu.org/soft
multilib.exp tests for multilib-altering flags in a board's
multilib_flags and skips the test, but if such flags appear in the
board's cflags, with the same distorting effects on tested multilibs,
we fail to skip the test.
Extend the skipping logic to board's cflags as well.
Regstrapping on x86
On May 31, 2024, Alexandre Oliva wrote:
>> I think we could drop this kluge entirely, clang 7 is old now, we
>> generally only support the most recent 3 or 4 clang versions.
> Fine with me, but I'd do that in a separate later patch, so that this
> goes in, and if it gets backported, it will cove
I am very sorry that I did not check the commit information carefully. The
statement is somewhat inaccurate.
> When the insn 1 and 2, 3 and 4 can be fusioned, then there is the
> following sequence:
>
> ;; insn |
> ;; 1 | sp=sp-0x18
> ;; + 2 | [sp+0x10]=ra
> ;; 3 | [sp+0x8]=s
From: Pan Li
As the middle support of .SAT_SUB committed, implement the unsigned
scalar int of .SAT_SUB for the riscv backend. Consider below example
code:
T __attribute__((noinline))\
sat_u_sub_##T##_fmt_1 (T x, T y) \
{ \
return (x - y) & (-(T)(x
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr112325.c:Add additional option --param
max-completely-peeled-insns=200 for power64*-*-*.
---
gcc/testsuite/gcc.dg/vect/pr112325.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/pr112325.c
b/gcc/testsuite/gcc.
Committed the series as the middle-end patch committed.
Pan
From: Li, Pan2
Sent: Monday, June 3, 2024 11:24 AM
To: juzhe.zh...@rivai.ai; gcc-patches
Cc: kito.cheng
Subject: RE: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD
form 1
Thanks Juzhe, will commit it after the middl
On Thu, 6 Jun 2024, Tobias Burnus wrote:
> GCC 15 now supports unified-shared memory and the tile/unroll constructs
> in OpenMP.
>
> Updates https://gcc.gnu.org/gcc-15/changes.html
> and https://gcc.gnu.org/projects/gomp/
Nice!
> Comments?
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/c
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, June 6, 2024 10:04 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com
Subject: Re: [PATCH v7] Match: Support more form for scalar unsign
Ajit Agarwal writes:
> On 06/06/24 8:03 pm, Richard Sandiford wrote:
>> Ajit Agarwal writes:
>>> On 06/06/24 2:28 pm, Richard Sandiford wrote:
Hi,
Just some comments on the fuseable_load_p part, since that's what
we were discussing last time.
It looks like this now r
On Thu, Jun 6, 2024 at 7:13 AM Rainer Orth
wrote:
>
> The Go testsuite's go.sum file ends in
>
> Couldn't determine version of
> /var/gcc/regression/master/11.4-gcc-64/build/gcc/gccgo
>
> on Solaris. It turns out this happens because gccgo -v is confused:
>
> [...]
> gcc version 15.0.0 20240531
On Thu, Jun 6, 2024 at 7:00 AM Rainer Orth
wrote:
>
> The index0-out.go test FAILs on Solaris (SPARC and x86, 32 and 64-bit),
> as well as several others:
>
> FAIL: ./index0-out.go execution, -O0 -g -fno-var-tracking-assignments
>
> The test SEGVs because it tries a stack acess way beyond the st
Hello Richard:
On 06/06/24 8:03 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 06/06/24 2:28 pm, Richard Sandiford wrote:
>>> Hi,
>>>
>>> Just some comments on the fuseable_load_p part, since that's what
>>> we were discussing last time.
>>>
>>> It looks like this now relies on:
>>>
>>
To test the theory that this issue was unrelated to my patch, I moved the
out_value_result definition into std/numeric and restored the version of
bits/ranges_algobase.h to the version in master. I kept the include line
"include " in std/numeric even though it wasn't being
used. With the incl
On Tue, 4 Jun 2024, Jakub Jelinek wrote:
> Hi!
>
> The following testcase ICEs in ipa-free-lang, because the
> fld_incomplete_type_of
> gcc_assert (TYPE_CANONICAL (t2) != t2
> && TYPE_CANONICAL (t2) == TYPE_CANONICAL (TREE_TYPE
> (t)));
> assertion doesn't hold.
>
> Pengxuan Zheng writes:
> > This patch adds vector floating point extend pattern for V2SF->V2DF
> > and
> > V4HF->V4SF conversions by renaming the existing
> > V4HF->aarch64_float_extend_lo_
> > pattern to the standard optab one, i.e., extend2. This
> > allows the vectorizer to vectorize certain
"Kewen.Lin" writes:
Hi Kewen,
> Nice! Looking forward to you pushing this new one (I'm withdrawing the
> original
> patch).
all pushed now - thanks for the original patch!
regards,
Gaius
PR middle-end/112600
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112600-2a.c: New test.
* gcc.target/i386/pr112600-2b.c: New test.
Tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/testsuite/gcc.target/i386/pr112600-2a.c
b/gcc/testsuite/gcc.target/i386/pr112600-2a.c
new f
Hi Torbjörn!
On Thu, 6 Jun 2024 at 18:47, Torbjörn SVENSSON
wrote:
>
> I would like to push this patch to the following branches:
>
> - releases/gcc-11
> - releases/gcc-12
> - releases/gcc-13
> - releases/gcc-14
> - trunk
>
> Ok?
>
> The problem was highlighted by https://linaro.atlassian.net/bro
On Thu, Jun 6, 2024 at 9:00 AM David Malcolm wrote:
>
> On Thu, 2024-06-06 at 08:40 -0700, Andrew Pinski wrote:
> > On Thu, Jun 6, 2024 at 6:02 AM Bert Wesarg
> > wrote:
> > >
> > > Dear David,
> > >
> > > On Tue, May 28, 2024 at 10:07 PM David Malcolm
> > > wrote:
> > > >
> > > > No functional
After r15-874-g9bda2c4c81b668, out of tree plugins won't compile
as the new libcpp header file label-text.h is not installed.
This adds the new header file to CPPLIB_H which is used for
the plugin headers to install.
Committed as obvious after a build and install and make sure
the new header file
No chance ?
On 22/05/2024 06:50, François Dumont wrote:
Ping ?
On 13/05/2024 06:33, François Dumont wrote:
libstdc++: [_Hashtable] Fix some implementation inconsistencies
Get rid of the different usages of the mutable keyword except in
_Prime_rehash_policy where it is preserved for ab
Ping the 3 patches for adding -mcpu=power11 support.
Patch #1: Add support for -mcpu=power11
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653552.html
Patch #2: Add tuning support for power11
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653550.html
Patch #3: Add power11 tests
https:
I would like to push this patch to the following branches:
- releases/gcc-11
- releases/gcc-12
- releases/gcc-13
- releases/gcc-14
- trunk
Ok?
The problem was highlighted by https://linaro.atlassian.net/browse/GNU-1239
--
Properly handle zero and sign extension for Armv8-M.baseline as
Cortex-M
On 6/2/24 21:01, Kewen Lin wrote:
This is to remove macros {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
defines in nios2 port.
gcc/ChangeLog:
* config/nios2/nios2.h (FLOAT_TYPE_SIZE): Remove.
(DOUBLE_TYPE_SIZE): Likewise.
(LONG_DOUBLE_TYPE_SIZE): Likewise.
Fine with me, but somewh
On Thu, 2024-06-06 at 08:40 -0700, Andrew Pinski wrote:
> On Thu, Jun 6, 2024 at 6:02 AM Bert Wesarg
> wrote:
> >
> > Dear David,
> >
> > On Tue, May 28, 2024 at 10:07 PM David Malcolm
> > wrote:
> > >
> > > No functional change intended.
> > >
> > > Successfully bootstrapped & regrtested on
On Thu, Jun 6, 2024 at 6:02 AM Bert Wesarg wrote:
>
> Dear David,
>
> On Tue, May 28, 2024 at 10:07 PM David Malcolm wrote:
> >
> > No functional change intended.
> >
> > Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
> > Pushed to trunk as r15-874-g9bda2c4c81b668.
> >
> > libcpp/
Richard Ball writes:
> v2: Change macro definition following internal discussion.
>
> __ARM_NEON_SVE_BRIDGE was missed in the original patch and is
> added by this patch.
>
> Ok for trunk and a backport into gcc-14?
Yes, thanks.
Richard
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-c.cc (
On Linux/x86_64,
4653b682ef161c3c2fc7bf8462b8f9206a1349e6 is the first bad commit
commit 4653b682ef161c3c2fc7bf8462b8f9206a1349e6
Author: Richard Biener
Date: Tue Mar 5 15:46:24 2024 +0100
Allow single-lane SLP in-order reductions
caused
FAIL: gcc.dg/vect/vect-cond-reduc-in-order-2-signe
On Linux/x86_64,
c989e59fc99d994159114304d4e715c72bedff0a is the first bad commit
commit c989e59fc99d994159114304d4e715c72bedff0a
Author: Hongyu Wang
Date: Wed Mar 27 10:13:06 2024 +0800
[APX CCMP] Support APX CCMP
caused
FAIL: gcc.target/i386/pr77881.c scan-assembler js[ \t].?L
with GC
v2: Change macro definition following internal discussion.
__ARM_NEON_SVE_BRIDGE was missed in the original patch and is
added by this patch.
Ok for trunk and a backport into gcc-14?
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
Add missing
On 06/06/2024 15:40, Richard Ball wrote:
> The CASE_VECTOR_SHORTEN_MODE query is missing some equals signs
> which causes suboptimal codegen due to missed optimisation
> opportunities. This patch also adds a test for thumb2
> switch statements as none exist currently.
>
> gcc/ChangeLog:
> PR
The CASE_VECTOR_SHORTEN_MODE query is missing some equals signs
which causes suboptimal codegen due to missed optimisation
opportunities. This patch also adds a test for thumb2
switch statements as none exist currently.
gcc/ChangeLog:
PR target/115353
* config/arm/arm.h (enum arm_a
Sandra Loosemore wrote:
On 6/6/24 06:06, Tobias Burnus wrote:
+@item I/O within OpenMP target regions and OpenACC compute regions
is supported
+ using the C library @code{printf} functions.
+ Additionally, the Fortran @code{print}/@code{write}
statements are
+ supported within O
Ajit Agarwal writes:
> On 06/06/24 2:28 pm, Richard Sandiford wrote:
>> Hi,
>>
>> Just some comments on the fuseable_load_p part, since that's what
>> we were discussing last time.
>>
>> It looks like this now relies on:
>>
>> Ajit Agarwal writes:
>>> + /* We use DF data flow because we c
On 6/6/24 06:06, Tobias Burnus wrote:
Hi Thomas,
regarding the commit r15-1070-g3a4775d4403f2e /
https://gcc.gnu.org/r15-1070
First, thanks for adding I/O support to nvptx offloading.
I have a wording nit, to be confirmed by a native speaker:
--- a/libgomp/libgomp.texi
+++ b/libgomp/libgom
The Go testsuite's go.sum file ends in
Couldn't determine version of
/var/gcc/regression/master/11.4-gcc-64/build/gcc/gccgo
on Solaris. It turns out this happens because gccgo -v is confused:
[...]
gcc version 15.0.0 20240531 (experimental) [master
a0d60660f2aae2d79685f73d568facb2397582d8] (G
On Thu, Jun 6, 2024 at 3:37 PM wrote:
>
> From: Pan Li
>
> After we support one gassign form of the unsigned .SAT_ADD, we
> would like to support more forms including both the branch and
> branchless. There are 5 other forms of .SAT_ADD, list as below:
>
> Form 1:
> #define SAT_ADD_U_1(T) \
It turns out target costing code looks at STMT_VINFO_MEMORY_ACCESS_TYPE
to identify operations from (emulated) gathers for example. This
doesn't work for SLP loads since we do not set STMT_VINFO_MEMORY_ACCESS_TYPE
there as the vectorization strathegy might differ between different
stmt uses. It s
The index0-out.go test FAILs on Solaris (SPARC and x86, 32 and 64-bit),
as well as several others:
FAIL: ./index0-out.go execution, -O0 -g -fno-var-tracking-assignments
The test SEGVs because it tries a stack acess way beyond the stack
area. As Ian analyzed in the PR, the testcase currently re
Hello Richard:
On 06/06/24 2:28 pm, Richard Sandiford wrote:
> Hi,
>
> Just some comments on the fuseable_load_p part, since that's what
> we were discussing last time.
>
> It looks like this now relies on:
>
> Ajit Agarwal writes:
>> + /* We use DF data flow because we change location rt
The following enables single-lane loop SLP discovery for non-grouped stores
and adjusts vectorizable_store to properly handle those.
For gfortran.dg/vect/vect-8.f90 we vectorize one additional loop,
not running into the "not falling back to strided accesses" bail-out.
I have not investigated in de
Hi Thomas,
This is v2 of the C/C++/middle-end parts of array/struct
support for OpenACC reductions.
The main changes are much fixed support for sub-arrays,
and some new testcases.
Tested on mainline using x86_64 host and nvptx/amdgcn offloading.
Will backport to upcoming omp/devel/gcc-14 branch a
From: Pan Li
After we support one gassign form of the unsigned .SAT_ADD, we
would like to support more forms including both the branch and
branchless. There are 5 other forms of .SAT_ADD, list as below:
Form 1:
#define SAT_ADD_U_1(T) \
T sat_add_u_1_##T(T x, T y) \
{ \
return (T)(x
On Thu, 6 Jun 2024, Richard Sandiford wrote:
> Pengxuan Zheng writes:
> > This patch adds the fix_truncv4sfv4hi2 (V4SF->V4HI) pattern which is
> > implemented
> > using fix_truncv4sfv4si2 (V4SF->V4SI) and then truncv4siv4hi2 (V4SI->V4HI).
> >
> > PR target/113882
> >
> > gcc/ChangeLog:
> >
>
Dear David,
On Tue, May 28, 2024 at 10:07 PM David Malcolm wrote:
>
> No functional change intended.
>
> Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
> Pushed to trunk as r15-874-g9bda2c4c81b668.
>
> libcpp/ChangeLog:
> * Makefile.in (TAGS_SOURCES): Add include/label-tex
Pengxuan Zheng writes:
> This patch adds the fix_truncv4sfv4hi2 (V4SF->V4HI) pattern which is
> implemented
> using fix_truncv4sfv4si2 (V4SF->V4SI) and then truncv4siv4hi2 (V4SI->V4HI).
>
> PR target/113882
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md (fix_truncv4sfv4hi2):
Richard Ball writes:
> __ARM_NEON_SVE_BRIDGE was missed in the original patch and is
> added by this patch.
>
> Ok for trunk and a backport into gcc-14?
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
> Add missing __ARM_NEON_SVE_BRIDGE.
After this
Hi!
On 2023-01-20T22:16:00+0100, Hi wrote:
> On 2023-01-20T22:04:02+0100, I wrote:
>> We've been (t)asked to enable (portions of) GCC/Fortran I/O for nvptx
>> offloading, which means building a normal (non-'LIBGFOR_MINIMAL')
>> configuration of libgfortran.
>
> This is achieved by 'nvptx, libgfort
Hi Thomas,
regarding the commit r15-1070-g3a4775d4403f2e / https://gcc.gnu.org/r15-1070
First, thanks for adding I/O support to nvptx offloading.
I have a wording nit, to be confirmed by a native speaker:
--- a/libgomp/libgomp.texi
+++ b/libgomp/libgomp.texi
...
+@item I/O within OpenMP tar
Hi!
On 2023-01-20T22:04:02+0100, I wrote:
> We've been (t)asked to enable (portions of) GCC/Fortran I/O for nvptx
> offloading, which means building a normal (non-'LIBGFOR_MINIMAL')
> configuration of libgfortran. One prerequisite patch, based on WIP work
> by Andrew Stubbs, is: "nvptx, libgcc: S
Tamar Christina writes:
> Hi All,
>
> I made an oversight in the previous patch, where I added a ?Upa
> alternative to the Upl cases. This causes it to create the tie
> between the larger register file rather than the constrained one.
>
> This fixes the affected patterns.
>
> Bootstrapped Regtest
Hi!
On 2022-12-23T14:35:16+0100, I wrote:
> On 2022-12-02T14:35:35+0100, I wrote:
>> On 2022-12-01T22:13:38+0100, I wrote:
>>> I'm working on support for global constructors/destructors with
>>> GCC/nvptx
>>
>> See "nvptx: Support global constructors/destructors via 'collect2'"
>> [posted before]
Hi!
On 2023-01-20T21:12:05+0100, I wrote:
> Re the newlib commit 05a2d7a8b3277b469e7cb121115bba398adc8559
> "nvptx: In offloading execution, map '_exit' to 'abort' [GCC PR85463]"
> that I've just pushes to newlib main branch:
>
> On 2023-01-19T23:00:05+0100, I wrote:
>> This is still not properly
On 05/06/2024 17:07, Andre Vieira (lists) wrote:
> Hi,
>
> This patch adds missing assembly directives to the CMSE library wrapper to
> call functions with attribute cmse_nonsecure_call. Without the .type
> directive the linker will fail to produce the correct veneer if a call to
> this wrappe
Hi Andrew, hi Jakub, hello world,
Andrew Stubbs wrote:
Compared to the previous v3 posting of this patch, the enumeration of
the "ompx" allocators have been moved to start at "100"
100 is a bad value - as can be seen below.
As Jakub suggested at
https://gcc.gnu.org/pipermail/gcc-patches/202
Hi All,
I made an oversight in the previous patch, where I added a ?Upa
alternative to the Upl cases. This causes it to create the tie
between the larger register file rather than the constrained one.
This fixes the affected patterns.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issu
> I'd only keep the simplest one for now. More complex cases can be
> handled easily
> with using dominators but those might not always be available or up-to-date
> when
> doing match queries. So let's revisit when we run into a case where
> the simple form
> isn't enough.
Got it. Thanks, will
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, June 6, 2024 6:50 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; ubiz...@gmail.com
Subject: Re: [PATCH v2] Vect: Support IFN SAT_SU
On Thu, Jun 6, 2024 at 8:26 AM wrote:
>
> From: Pan Li
>
> This patch would like to support the .SAT_SUB for the unsigned
> vector int. Given we have below example code:
>
> void
> vec_sat_sub_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
> {
> for (unsigned i = 0; i < n; i++)
>
On Thu, Jun 6, 2024 at 3:19 AM Li, Pan2 wrote:
>
> Hi Richard,
>
> After revisited all the comments of the mail thread, I would like to confirm
> if my understanding is correct according to the generated match code.
> For now the generated code looks like below:
>
> else if (gphi *_a1 = dyn_cast
Pengxuan Zheng writes:
> This patch adds vector floating point extend pattern for V2SF->V2DF and
> V4HF->V4SF conversions by renaming the existing
> aarch64_float_extend_lo_
> pattern to the standard optab one, i.e., extend2. This allows the
> vectorizer to vectorize certain floating point wideni
On Fri, May 24, 2024 at 9:27 AM Richard Biener wrote:
>
> On Thu, 23 May 2024, Manolis Tsamis wrote:
>
> > This pass detects cases of expensive store forwarding and tries to avoid
> > them
> > by reordering the stores and using suitable bit insertion sequences.
> > For example it can transform th
This pass detects cases of expensive store forwarding and tries to avoid them
by reordering the stores and using suitable bit insertion sequences.
For example it can transform this:
strbw2, [x1, 1]
ldr x0, [x1] # Expensive store forwarding to larger load.
To:
ldr
YunQiang Su writes:
> YunQiang Su 于2024年5月29日周三 10:02写道：
>>
>> Richard Sandiford 于2024年5月29日周三 05:28写道：
>> >
>> > YunQiang Su writes:
>> > > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
>> > > toolchain,
>> > > the final fallback is `as/ld` of system. In fact, we can hav
Thursday, June 6, 2024 1:42 AM
Jonathan Yong <10wa...@gmail.com> wrote:
>
> Where is HAVE_64BIT_POINTERS used?
>
Sorry, it was missed in the posted changes for review.
Regards,
Evgeny
diff --git a/gcc/config/mingw/mingw32.h b/gcc/config/mingw/mingw32.h
index 8a6f0e8e8a5..0c9d5424942 100644
---
Hi,
Just some comments on the fuseable_load_p part, since that's what
we were discussing last time.
It looks like this now relies on:
Ajit Agarwal writes:
> + /* We use DF data flow because we change location rtx
> + which is easier to find and modify.
> + We use mix of rtl-ssa d
Enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc.
gcc/ChangeLog:
* config/i386/i386-opts.h (enum apx_features):Add apx_zu.
* config/i386/i386.h (TARGET_APX_ZU): Define.
* config/i386/i386.md (*imulhizu): New define_insn.
(*setcc__zu): Ditto.
* config/i3
GCC 15 now supports unified-shared memory and the tile/unroll constructs
in OpenMP.
Updates https://gcc.gnu.org/gcc-15/changes.html
and https://gcc.gnu.org/projects/gomp/
Comments?
Tobias
gcc-15/changes.html + projects/gomp: update for new OpenMP features
GCC 15 now supports unified-shared mem
Hi,
I wasn't aware that I needed to regenerate the opt urls when
adding an option. For this patch I did it now.
I suppose this doesn't require an extra OK but I'm going to
wait some minutes before applying still.
Regards
Robin
gcc/ChangeLog:
* config/riscv/riscv.opt.urls: Regenerate.
Thanks, this is the patch I'm going to check-in.
For general ccmp scenario, the tree sequence is like
_1 = (a < b)
_2 = (c < d)
_3 = _1 & _2
current ccmp expanding will try to swap compare order for _1 and _2,
compare the expansion cost/cost2 for expanding _1 or _2 first, then
return the sequenc
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