Ping.
Regards,
Andrew
> -Original Message-
> From: Andrew Bennett
> Sent: 28 August 2015 16:50
> To: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard
> library support check th
> -Original Message-
> From: Matthew Fortune
> Sent: 05 May 2016 10:44
> To: Andrew Bennett; gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] MIPS: Ensure that lo_sums do not contain an unaligned
> symbol
>
> Hi Andrew,
>
> Thanks for working on this it is a pai
Hi,
Currently the mips_print_operand_address function ignores its mode argument,
and when it calls
mips_classify_address it forces the mode argument to be the machine's word
mode. This patch
makes mips_print_operand_address pass the mode argument provided to it to
mips_classify_address,
so
Hi,
In MIPS (and similarly for other RISC architectures) to load an absolute
address of an object
requires a two instruction sequence: one instruction to load the high part of
the object's address,
and one instruction to load the low part of the object's address. Typically
the result from
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: 03 February 2016 22:45
> To: Andrew Bennett
> Cc: Matthew Fortune; Steve Ellcey; gcc-patches@gcc.gnu.org;
> c...@codesourcery.com
> Subject: Re: [Patch, MIPS] Patch for P
> -Original Message-
> From: Matthew Fortune
> Sent: 30 January 2016 16:46
> To: Richard Sandiford; Steve Ellcey
> Cc: gcc-patches@gcc.gnu.org; c...@codesourcery.com; Andrew Bennett
> Subject: RE: [Patch, MIPS] Patch for PR 68400, a mips16 bug
>
> Ric
> This is OK now.
Committed as SVN 232980.
Regards,
Andrew
Ping.
Andrew
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
> Behalf Of Andrew Bennett
> Sent: 02 September 2015 14:55
> To: Matthew Fortune; gcc-patches@gcc.gnu.org
> Cc: Moore, Catherine (catherine_mo...@mentor.
> > diff --git a/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> > b/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> > index 0890ffa..20c26ca 100644
> > --- a/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> > +++ b/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> > @@ -1,6 +1,7 @@
> > /* { dg-do
Yes, this looks OK.
Committed as SVN 227299.
Regards,
Andrew
I had some comments on this that I hadn't got round to posting. The fix in
this patch is not general enough as the missing header problem comes in
two (related) forms:
1) Using the new MTI and IMG sysroot layout we can end up with GCC looking
for headers in a sysroot that simply does not
Hi,
The MIPS p5600-bonding.c test is currently failing for the n32 and n64
ABIs. The test is checking if the load/store bonding patterns correctly
match sequences of load/store instructions. There are currently no load/store
bonding patterns to match DI mode values. For the n32 and n64 ABIs
Hi,
The lo register is not listed in the clobber list in the inline asm statement
for the madd-8.c and msub-8.c testcases. This means that when building for the
n64 ABI GCC is free to use the lo register instead of the stack when
saving/restoring
the clobbered registers. Then then means that
Hi,
The recent changes to the MIPS GCC Linux sysroot
(https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01014.html) have meant that
the include directory is now not global and is provided only for each
multi-lib configuration. This means that for any test in the MIPS GCC
Testsuite that requires
Ok to commit?
Yes, this is OK.
Committed as SVN 225813.
Regards,
Andrew
Yeah, I agree that this doesn't really fit the model that well,
but like you say, we're stretching the logic a bit :-). When I wrote it,
the architectures formed a nice tree in which moving to leaf nodes only
added features. So in the pre-r6 days:
# Handle dependencies between the
Hi,
I have noticed that in the mips.exp dg-option handling code the isa and
arch_test_option_p variables are not updated after the pre-arch to arch
dependency handling. This means that if this code changes the
architecture the post-arch dependency handling code (which relies on
Yes, this is OK.
Committed as SVN 225536.
Regards,
Andrew
testsuite/
* gcc.target/mips/branch-2.c: Change NOMIPS16 to
NOCOMPRESSION.
* gcc.target/mips/branch-3.c: Ditto
* gcc.target/mips/branch-4.c: Ditto.
* gcc.target/mips/branch-5.c: Ditto.
* gcc.target/mips/branch-6.c: Ditto.
* gcc.target/mips/branch-7.c: Ditto.
I'm not sure this is the right approach here. If we get a jraddiusp then the
problem that the test is trying to cover can't possibly happen anyway.
(The test is checking if a load and final stack adjustment are ever re-
ordered
from what I can see.)
I'd just mark the test as
I see that you are naming these tests after the original branch-number tests
that they were derived from.
I think it would be better to keep all of the microMIPS tests named umips-???.
I don't think preserving the original number is important.
I have named the microMIPS tests umips-branch-???
Hi Andrew,
Instead of adding the -mno-micromips option to dg-options, please change the
MIPS16 attribute to NOCOMPRESSION.
Index: gcc.target/mips/no-smartmips-lwxs.c
===
--- gcc.target/mips/no-smartmips-lwxs.c (revision
Hi,
When building the call-[1,5,6].c tests for micromips the jrc rather than the
jr instruction is used to call the tail* functions.
I have updated the test output to allow the jrc instruction to be matched.
I have tested this on the mips-mti-elf target using
OK.
Committed as SVN 225516.
Regards,
Andrew
There is a follow-up patch that I will be working on that will correctly
update the other
branch tests to correctly test out of range branch behaviour for
micromips. Currently these
are passing because the mips branch range offset is large enough. These
offsets will
need to be reduced for
Hi,
The near-far-3.c test is failing for micromips because it is expecting the call
to near_func to be performed by a jal instruction, but for micromips this is
done
by a jals instruction.
I have updated the expected test output to deal with this case. I have tested
this on the mips-mti-elf
Hi,
The LWXS instruction is part of the micromips ISA which means it is
valid to generate it for the no-smartmips-lwxs.c testcase. I have
updated the dg-options for the test to ensure that it does not
generate micromips code.
I have tested this on the mips-mti-elf target using
Hi,
The stack-1.c testcase fails when being compiled for micromips with the -O0
optimization level. The reason is the testcase is expecting the following
sequence at the end of the function:
addiu $sp,$sp,16
jrc $31
But for micromips it generates the following:
OK.
Committed as SVN 225457.
Regards,
Andrew
Hi,
The current branch range tests assume that the MIPS branch instructions
have a 16 bit branch offset which is shifted by 2. Unfortunately for microMIPS
this offset is shifted by 1 which reduces the branch range and is causing the
branch-[2,4,6,10,12].c tests to fail.
The following
OK. Please install.
Committed as SVN revision 224064.
Hi Jeff,
Are you also happy for me to backport the patch on to the 4.9 and 5 branches?
Many thanks,
Andrew
OK. Please install.
Committed as SVN revision 224064.
Many thanks,
Andrew
Hi,
In the plus_constant function in explow.c the code to update a constant pool
value
does not deal with the case where the value returned from force_const_mem is a
NULL_RTX. This occurs for the MIPS target because its
cannot_force_const_mem target function does not allow constants (so that
Hi,
The call-saved-{4-6}.c tests in the mips testsuite fail for micromips. The
reason is
that micromips uses the swm and lwm instructions to save/restore the call-saved
registers
rather than using the sw and lw instructions. The swm and lwm instructions
only list
the range of registers to
Yes, removing the second NOP is worth the additional effort.
The updated patch is below.
Ok to commit?
Regards,
Andrew
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 02268f3..368c6f0 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -12997,7
Please rephrase the comment along the lines of my previous suggestion.
This wording is too complex IMO.
The patch containing the updated comment (which also keeps within 72 columns)
is below.
Ok to commit?
Regards,
Andrew
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index
Hi,
The atomic-compare-exchange-3.c and atomic-op-3.c tests are failing when
using the -mfix-r1 option. This is due to the fact that the delay
slot of the branch instruction that checks if the atomic operation was
not successful can be filled with an operation that returns the output
-Original Message-
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
Sent: 18 November 2014 13:48
To: Andrew Bennett
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] If using branch likelies in MIPS sync code fill the delay
slot with a nop
On Tue, 18 Nov 2014, Andrew
OK, this does look to me like the correct way to address the issue, but
where is the second NOP that you previously mentioned? I fail to see it
here and this code can't be made any better, there isn't anything you
could possibly schedule into the delay slot as there is nothing else to
do in
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
On Tue, 18 Nov 2014, Andrew Bennett wrote:
Produces (for the atomic operation):
.setnoat
sync
1:
ll $3,0($5)
and $1,$3,$4
bne $1,$7,2f
and $1,$3,$6
FWIW, since regenerated files are often not posted as part of the patch,
I'd just assumed the committer would do that. I should have checked the
changelog though...
Thats fine. I will remember in future not to include regenerated files in
my patches.
Secondly, I have changed invoke.texi
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
Behalf Of Richard Sandiford
Sent: 28 May 2014 10:42
To: Jaydeep Patil
Cc: Rich Fuhler; Matthew Fortune; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH][MIPS] P5600 scheduling
Jaydeep
Hi,
This patch adds myself to the MAINTAINERS file. Commmitted as r211167.
The ChangeLog and patch are shown below.
Regards,
Andrew
Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814
www.imgtec.com
2014-06-03 Andrew Bennett
-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: 08 May 2014 20:28
To: Andrew Bennett
Cc: gcc-patches@gcc.gnu.org; Matthew Fortune; Saeed Ghazanfar; Rich Fuhler
Subject: Re: [PATCH] Add support for MIPS r3 and r5
Andrew Bennett andrew.benn
-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: 09 May 2014 12:07
To: Andrew Bennett
Cc: gcc-patches@gcc.gnu.org; Matthew Fortune; Saeed Ghazanfar; Rich Fuhler
Subject: Re: [PATCH] Add support for MIPS r3 and r5
Andrew Bennett andrew.benn
Hi,
This patch adds a GCC MIPS command line option (-mxpa) to enable/disable
support for the eXtended Physical Address (XPA) instructions within
the assembler.
The ChangeLog and patch are shown below.
Many thanks,
Andrew
* doc/invoke.texi: Document -mxpa and -mno-xpa MIPS command
Richard Sandiford rdsandif...@googlemail.com writes:
Andrew Bennett andrew.benn...@imgtec.com writes:
Hi,
I have noticed that a patch was placed in bugzilla to do this change, but
it
does not appear to have been pushed. I was wondering if anyone could
comment
why this is the case
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