> On 5 Jun 2018, at 19:28, James Greenhalgh wrote:
>
> On Tue, Jun 05, 2018 at 11:32:06AM -0500, Kyrill Tkachov wrote:
>>
>> On 04/06/18 18:40, Kyrill Tkachov wrote:
>>> Hi all,
>>>
>>> This patch adds support for generating LDPs and STPs of Q-registers.
>>> This allows for more compact code g
> On 10 Nov 2016, at 18:14, Wilco Dijkstra wrote:
>
> I think the XGene-1 scheduler might need a similar change as currently all
> AArch64
> shifts are modelled as 2-cycle operations.
Thanks for the heads-up. We’ll indeed need to update this.
Regards,
Philipp.
> On 10 Jun 2016, at 01:28, Jim Wilson wrote:
>
> On Tue, May 31, 2016 at 2:56 AM, James Greenhalgh
> wrote:
>> As you're proposing to have this on by default, I'd like to give a chance
>> to hear whether there is consensus as to this being the right choice for
>> the thunderx, xgene1, exynos-m
James,
ok from our side—good to see that this also benefits the A57.
Best,
Philipp.
> On 11 Jan 2016, at 13:04, James Greenhalgh wrote:
>
>
> Hi,
>
> I've seen a couple of large performance issues caused by expanding
> the high-precision reciprocal square root for Cortex-A57, so I'd like
> t
James,
On 29 Jun 2015, at 13:36, James Greenhalgh wrote:
>
> On Mon, Jun 29, 2015 at 10:18:23AM +0100, Kumar, Venkataramanan wrote:
>>
>>> -Original Message-
>>> From: Dr. Philipp Tomsich [mailto:philipp.toms...@theobroma-systems.com]
>>> Sen
ikt , I have ICE for 444.namd with your patch, not sure if something
> wrong in my local tree.
>
> Regards,
> Venkat.
>
>> -Original Message-
>> From: pins...@gmail.com [mailto:pins...@gmail.com]
>> Sent: Sunday, June 28, 2015 8:35 PM
>> To: Kumar, Venkata
Kumar,
what is the relative gain that you see on Cortex-A57?
Thanks,
Philipp.
> On 25 Jun 2015, at 17:35, Kumar, Venkataramanan
> wrote:
>
> Changing to "1 step for float" and "2 steps for double" gives better gains
> now for gromacs on cortex-a57.
>
> Regards,
> Venkat.
>> -Original M
er [mailto:benedikt.hu...@theobroma-systems.com]
>> Sent: Wednesday, June 24, 2015 12:11
>> To: Dr. Philipp Tomsich
>> Cc: Evandro Menezes; gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH] [aarch64] Implemented reciprocal square root (rsqrt)
>> estimation in -ffast-math
>>
Evandro,
We’ve seen a 28% speed-up on gromacs in SPECfp for the (scalar) reciprocal sqrt.
Also, the “reciprocal divide” patches are floating around in various of our
git-tree, but
aren’t ready for public consumption, yet… I’ll leave Benedikt to comment on
potential
timelines for getting that
> On 13 Feb 2015, at 11:14, Richard Earnshaw
> wrote:
>
>> Is this ok?
>
> The repetitive nature of all these new cpus being added looks rather
> wooden. I think it would be better to merge them into one change block,
> that lists all the cpus and their internal names, then mentions once at
>
Richard,
Thanks for catching this.
Your change is optimal for X-Gene 1.
—Phil.
> On 15 Jan 2015, at 19:51, Richard Earnshaw wrote:
>
> The recent xgene tuning parameters merge broke the ARM bootstrap, since
> the tables have been extended by an additional parameter giving:
>
> gcc/config/arm/
Great. I should have an update patch-set ready & tested later tonight.
Best,
Phil.
> On 13 Jan 2015, at 15:18, Andrew Pinski wrote:
>
> On Tue, Jan 13, 2015 at 6:13 AM, Marcus Shawcroft
> wrote:
>> On 11 January 2015 at 02:37, Andrew Pinski wrote:
>>> On Tue, Nov 11, 2014 at 6:47 AM, Marcus S
Should I revise, or do will you just drop tje line when applying when applying
this?
Thanks,
Phil.
> On 05 Dec 2014, at 18:23, Marcus Shawcroft wrote:
>
> On 21 November 2014 at 18:44, Philipp Tomsich
> wrote:
>
>> +;; Machine description for AppliedMicro xgene1 core.
>> +;; Copyright (C) 20
Kyrill,
> I don't mind it being in config/arm if you plan to wire it up later, good to
> know.
> Another comment inline….
I’ll clean up the missing xgene1_ and the mistyped xgene_ prefix and resubmit.
>> +(define_insn_reservation "div" 2
>> + (and (eq_attr "tune" "xgene1")
>> + (eq_attr
Kyrill,
The XGene-cores all support AArch32.
We plan to wire this up, but I’d like to merge this as-is (i.e. without wiring
it up for AArch32) initially, as we haven’t done the same amount of QA on these
with AArch32 as with AArch64.
Do you have any issue with this going into the config/arm-dir
On 28 May 2014, at 16:25 , Gopalasubramanian, Ganesh
wrote:
> Hi Philipp,
>
>> These changes look good to me.
>> We'll try them out on the benchmarks that caused us to add prefetching in
>> the first place.
>
> If you are OK, I would like to get these changes upstreamed.
Sorry for the delay
Ganesh,
On 28 Feb 2014, at 10:13 , Gopalasubramanian, Ganesh
wrote:
> I also have attached a patch that implements the following.
> * Prefetch with immediate offset in the range 0 to 32760 (multiple of 8).
> Added a predicate for this.
> * Prefetch with immediate offset - in the range
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