From: "Dragan Mladjenovic"
Greetings,
These patches enable emitting .note.GNU-stack by default on mips linux targets.
First one enables it unconditionally for soft-float builds while the second one
enables it for hard-float build if gcc is configured against the future version
of
From: "Dragan Mladjenovic"
gcc/ChangeLog:
2019-08-05 Dragan Mladjenovic
* config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
TARGET_SOFT_FLOAT.
* config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
(mips_asm_file_end): New function. D
From: "Dragan Mladjenovic"
libgcc/ChangeLog:
2019-08-05 Dragan Mladjenovic
* config/mips/gnustack.h: Check for TARGET_LIBC_GNUSTACK also.
gcc/ChangeLog:
2019-08-05 Dragan Mladjenovic
* config.in: Regenerated.
* config/mips/linux.h (NEED_INDICATE_
On 09.08.2019. 23:31, Jeff Law wrote:
> On 8/5/19 4:47 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic"
>>
>> gcc/ChangeLog:
>>
>> 2019-08-05 Dragan Mladjenovic
>>
>> * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Def
PM
To: Dragan Mladjenovic; gcc-patches@gcc.gnu.org
Cc: Matthew Fortune
Subject: Re: [MIPS] Fix for the wrong argument sequence in MSA builtin for
FMADD/MADDV family.
On 5/22/19 12:13 AM, Dragan Mladjenovic wrote:
> Hi all,
>
> This patch makes the behavior of __builtin_msa_ fmadd/fmsub/m
From: "Dragan Mladjenovic"
This patch prevents merging of CALL instructions that that have different
REG_CALL_DECL notes attached to them.
On most architectures this is not an important distinction. Usually instruction
patterns
for calls to different functions reference different SY
ed by ipa-ra.
As per comment form Richard Sandiford, this version compares reg usage for both
call
instruction instead of shallow comparing the notes. Tests updated accordingly.
gcc/ChangeLog:
2019-07-09 Dragan Mladjenovic
* cfgcleanup.c (old_insns_match_p): Check if used hard regs s
On 09.07.2019. 23:21, Jeff Law wrote:
> On 7/9/19 2:06 PM, Dragan Mladjenovic wrote:
>> This patch prevents merging of CALL instructions that that have different
>> REG_CALL_DECL notes attached to them.
>>
>> On most architectures this is not an important distincti
From: "Dragan Mladjenovic"
Hi all,
For TARGET_FLOATXX the odd-numbered FP registers in SFmode are
HARD_REGNO_CALL_PART_CLOBBERED. This causes dwarf_frame_reg_mode to fall
back to VOIDmode and for __builtin_init_dwarf_reg_size_table to fill them
as zero sized.
This prevents libgcc&
Ping.
From: Dragan Mladjenovic
Sent: Thursday, May 9, 2019 12:29 PM
To: gcc-patches@gcc.gnu.org
Cc: Dragan Mladjenovic; Jakub Jelinek; Matthew Fortune
Subject: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with -mfpxx
From: "Dragan Mladje
Thank you.
What can I do to ensure this gets back-ported as further back as possible? I
assume that it can go all the way back to gcc 7 branch.
Best regards,
Dragan
From: Jeff Law
Sent: Friday, May 17, 2019 6:28 PM
To: Dragan Mladjenovic; gcc-patches
Thank you.
From: Jeff Law
Sent: Monday, May 20, 2019 9:13 PM
To: Dragan Mladjenovic; gcc-patches@gcc.gnu.org
Cc: Jakub Jelinek; Matthew Fortune
Subject: Re: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with
-mfpxx
On 5/19/19 4:18 AM, Dragan
Robert Suchanek
* gcc/config/mips/mips.c (mips_expand_builtin_insn): Swap the 1st
and 3rd operands of the fmadd/fmsub/maddv builtin.
gcc/testsuite/ChangeLog:
2019-05-20 Dragan Mladjenovic
* gcc.target/mips/msa-fmadd.c: New.
---
gcc/config/mips/mips.c
On 24.07.2019. 20:57, Jeff Law wrote:
> On 7/17/19 2:29 AM, Dragan Mladjenovic wrote:
>>
>>
>> On 09.07.2019. 23:21, Jeff Law wrote:
>>> On 7/9/19 2:06 PM, Dragan Mladjenovic wrote:
>>>> This patch prevents merging of CALL instructions that that have diff
From: "Dragan Mladjenovic"
This fixes the issue by checking that addr's base reg is not part of dest
multiword reg instead just checking the first reg of dest.
gcc/ChangeLog:
2019-09-25 Dragan Mladjenovic
PR target/91769
* config/mips/mips.c (mips_s
CC: YunQiang Su
On 25.09.2019. 09:16, Dragan Mladjenovic wrote:
> From: "Dragan Mladjenovic"
>
> This fixes the issue by checking that addr's base reg is not part of dest
> multiword reg instead just checking the first reg of dest.
>
> gcc/ChangeLog:
&
On 01.10.2019. 21:37, Jeff Law wrote:
> On 9/25/19 1:16 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic"
>>
>> This fixes the issue by checking that addr's base reg is not part of dest
>> multiword reg instead just checking the first reg of d
On 06.10.2019. 08:43, Paul Hua wrote:
> Hi:
>
> The testsuite has a typo in "dg-final scan-assembler", s/mthc1/mtc1/.
>
Hi,
I think I know what is happening here. My testing setup defaults to
-mfpxx and yours probably to -mfp32. I should have probably tightened
the test up to require R2 isa
On 01.10.2019. 21:35, Jeff Law wrote:
> On 9/6/19 4:23 AM, Dragan Mladjenovic wrote:
>> On 24.07.2019. 20:57, Jeff Law wrote:
>>> On 7/17/19 2:29 AM, Dragan Mladjenovic wrote:
>>>>
>>>>
>>>> On 09.07.2019. 23:21, Jeff Law wrote:
>>
On 10.08.2019. 00:15, Joseph Myers wrote:
> On Fri, 9 Aug 2019, Jeff Law wrote:
>
>>> 2019-08-05 Dragan Mladjenovic
>>>
>>> * config.in: Regenerated.
>>> * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
>>> for TAR
On 22.02.2020. 13:25, Gerald Pfeifer wrote:
On Fri, 24 Jan 2020, Dragan Mladjenovic wrote:
From: "Dragan Mladjenovic"
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index ef27c9b..7736990 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
On 16.11.2019. 00:33, Jeff Law wrote:
> On 11/15/19 10:27 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic"
>>
>> This patch tightens the instruction definitions to make sure
>> that MSA branch instructions cannot be put into delay slots and
On 07.11.2019. 18:05, Dragan Mladjenovic wrote:
> On 01.11.2019. 11:32, Dragan Mladjenovic wrote:
>> On 10.08.2019. 00:15, Joseph Myers wrote:
>>> On Fri, 9 Aug 2019, Jeff Law wrote:
>>>
>>>>> 2019-08-05 Dragan Mladjenovic
>>>>>
&g
On 07.12.2019. 19:33, Jeff Law wrote:
> On Thu, 2019-11-07 at 17:05 +0000, Dragan Mladjenovic wrote:
>> On 01.11.2019. 11:32, Dragan Mladjenovic wrote:
>>> On 10.08.2019. 00:15, Joseph Myers wrote:
>>>> On Fri, 9 Aug 2019, Jeff Law wrote:
>>>
From: "Dragan Mladjenovic"
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index ef27c9b..7736990 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -623,7 +623,14 @@ a work-in-progress.
-
+MIPS
+
+ The mips*-*-linux* targets now m
t; (The other change in gcc/configure seems to be due to Andrew Burgess's
> e7c26e04b2dd6266d62d5a5825ff7eb44d1cf14e )
>
> Tobias
>
> PS: The following was committed as 54b3d52c3cca836c7c4c08cc9c02eda6c096372a
>
> On 1/23/20 11:58 AM, Dragan Mladjenov
From: Dragan Mladjenovic
Commit 54b3d52 ("Emit .note.GNU-stack for hard-float linux targets.")
was missing generated files. Add them now.
gcc/ChangeLog:
2020-01-30 Dragan Mladjenovic
* config.in: Regenerated.
* configure: Regenerated.
---
gcc/ChangeLog | 5
On 29.01.2020. 22:57, Dragan Mladjenovic wrote:
On 29.01.2020. 12:06, Tobias Burnus wrote:
Hi Dragan,
I think your committed patch was incomplete – at least I see the
following bits when running --enable-maintainer-mode (see attachment,
line numbers wrong as I edited my changes out).
Can you
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b5cbcebf..1e1eaf43 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -692,7 +692,17 @@ a work-in-progress.
-
+ MIPS
+
+The mips*-*-linux* targets now mark object files with
+ appropr
On 3/30/2020 17:39, Jeff Law wrote:
On Sun, 2020-03-29 at 22:33 +0200, Dragan Mladjenovic wrote:
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b5cbcebf..1e1eaf43 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -692,7 +692,17 @@ a work-in
On 01.11.2019. 11:32, Dragan Mladjenovic wrote:
> On 10.08.2019. 00:15, Joseph Myers wrote:
>> On Fri, 9 Aug 2019, Jeff Law wrote:
>>
>>>> 2019-08-05 Dragan Mladjenovic
>>>>
>>>> * config.in: Regenerated.
>>>> * config/mi
From: "Dragan Mladjenovic"
This was dormant for quite some time, but it started happening for me
on gcc.c-torture/compile/pr65153.c sometime after r276645 for -mabi=32 linux
runs.
The pattern accepts any SMALL_OPERAND constant value while it asserts during
the final
that the value
On 12.11.2019. 16:29, Jeff Law wrote:
> On 11/12/19 7:56 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic"
>>
>> This was dormant for quite some time, but it started happening for me
>> on gcc.c-torture/compile/pr65153.c sometime after r276645 f
From: "Dragan Mladjenovic"
This patch tightens the instruction definitions to make sure
that MSA branch instructions cannot be put into delay slots and have their
delay slots eligible for being filled. Also, MSA *div*3 patterns use MSA
branches for zero checks but are not marke
Hi,
Looks fine to me. If possible, maybe it should even be back-ported to
stable branches.
Not sure if MIPS assembly sources (if any) in musl would need explicit
.note.GNU-stack
to complement this?
Best regards,
Dragan
On 16-Nov-21 06:13, Ilya Lipnitskiy wrote:
musl only uses PT_GNU_STA
This patch allows a function to request clearing of all instruction and
execution
hazards upon normal return via __attribute__ ((use_hazard_barrier_return)).
2017-04-25 Prachi Godbole
gcc/
* config/mips/mips.h (machine_function): New variable
use_hazard_barrier_return_p.
> -Original Message-
> From: Andrew Pinski [mailto:pins...@gmail.com]
> Sent: 16 August 2021 21:17
> To: Dragan Mladjenovic
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [MIPS] Hazard barrier return support
>
> On Mon, Aug 16, 2021 at 7:43 AM Dragan Mla
> -Original Message-
> From: Dragan Mladjenovic
> Sent: 16 August 2021 22:40
> To: 'Andrew Pinski'
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] [MIPS] Hazard barrier return support
>
>
>
> > -Original Message-
> &
Since 'Remove obsolete IRIX 6.5 support' [1] we only use
gp-relative jump-tables for PIC code. We can fall back to
default behaviour for asm_function_rodata_section.
[1] https://gcc.gnu.org/ml/libstdc++/2012-03/msg00067.html
2018-06-04 Dragan Mladjenovic
gcc/
* config/m
From: Jeff Law [mailto:jeffreya...@gmail.com]
Sent: 19 August 2021 18:03
To: Dragan Mladjenovic ;
gcc-patches@gcc.gnu.org
Cc: Andrew Pinski
Subject: Re: [PATCH][MIPS] Remove TARGET_ASM_FUNCTION_RODATA_SECTION
> On 8/19/2021 6:11 AM, Dragan Mladjenovic wrote:
> > Since 'Remove
2021-08-21 Dragan Mladjenovic
ChangeLog:
* MAINTAINERS: Add myself for write after approval.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7b03fc25f4d..b8d5f16f85f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -531,6 +531,7
> -Original Message-
> From: Dragan Mladjenovic
> Sent: 17 August 2021 17:59
> To: 'Andrew Pinski'
> Cc: 'gcc-patches@gcc.gnu.org'
> Subject: RE: [PATCH] [MIPS] Hazard barrier return support
>
>
>
> > -----Original Message-
)
(Mihailo Stojanovic)
(Dragan Mladjenovic)
Avoid references to register names in instruction output patterns
Make mips-classic.md entry point for mips*-*-* targets
Add nanoMIPS support
Add test cases for nanoMIPS
Fix unhelpful messages for disabled options
Enable MIPS DSP rev3 ASE for
This allows us to choose the different names if needed in the future.
gcc/ChangeLog:
* config/mips/mips.c (mips_print_operand_punctuation):
Handle '&' punctuation.
(mips_output_probe_stack_range): Use '%.' instead of $0.
* config/mips/mips.h (GLOBAL_POINTER_REGNUM)
Make parts of the code and options conditional on compile-time defines.
gcc/ChangeLog:
* config/mips/mips.h
(MIPS_SUPPORT_DSP, MIPS_SUPPORT_PS_3D,
MIPS_SUPPORT_MSA, MIPS_SUPPORT_LOONGSON
MIPS_SUPPORT_MICROMIPS, MIPS_SUPPORT_LEGACY
MIPS_SUPPORT_FRAME_HEADER_
Firstly, the option handling was building suggestions without checking
if an option is disabled. This could have caused other unhelpful
messages for other mistyped options.
Secondly, the key issue here appears to be the lack of CL_JOINED flag
for the false 'Condition' i.e. an option is disabled b
gcc/ChangeLog:
* doc/extend.texi: Add nanoMIPS Function Attributes,
nanoMIPS Built-in Functions and nanoMIPS DSP Built-in Functions.
* doc/invoke.texi: Add nanoMIPS Options.
* doc/md.texi: Add nanoMIPS constraints.
---
gcc/doc/extend.texi | 124 +++
gcc
gcc/ChangeLog:
* config/mips/mips-dsp.md (mips_bposge):
Output bposgec for TARGET_DSPR3.
* config/mips/mips.c (mips_output_move):
Use $ac0 for $lo if base isa doesn't have md registers.
(mips_option_override) [TARGET_DSPR3]:
Enable TARGET_DSP and TA
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