2017-08-22 9:18 GMT+01:00 Jiong Wang :
> On 10/08/17 17:39, Jiong Wang wrote:
>>
>> Hi,
>>
>> A new vendor CFA DW_CFA_AARCH64_negate_ra_state was introduced for
>> ARMv8.3-A
>> return address signing, it is multiplexing DW_CFA_GNU_window_save in CFA
>
On 10/08/17 17:39, Jiong Wang wrote:
Hi,
A new vendor CFA DW_CFA_AARCH64_negate_ra_state was introduced for
ARMv8.3-A
return address signing, it is multiplexing DW_CFA_GNU_window_save in
CFA vendor
extension space.
This patch adds necessary code to make it available to external, the
Jiong Wang
include/
* dwarf2.def (DW_CFA_AARCH64_negate_ra_state): New DW_CFA_DUP.
* dwarf2.h (DW_CFA_DUP): New define.
libiberty/
* dwarfnames.c (DW_CFA_DUP): New define.
diff --git a/include/dwarf2.def b/include/dwarf2.def
index a91e9439cd82f3bb9fdddc14904114e5490c1af6
On 15/06/17 15:12, Wilco Dijkstra wrote:
This results in smaller code and unwind info.
I have done a quick test on your updated patch through building latest linux
kernel.
Dwarf frame size improved (~ 5% smaller) as using sp to address locals doesn't
need to update CFA register etc.
Though th
On 15/03/17 15:34, Rainer Orth wrote:
Hi Jiong,
Subject: [PATCH] testsuite, 79356
As stated in the PR (and elsewhere), this test now passes on aarch64,
ia64, mips, powerpc, sparc, and s390x. This patch disables the xfails
for those targets.
gcc/testsuite/
PR testsuite/79356
On 10/03/17 15:26, Segher Boessenkool wrote:
On Fri, Mar 10, 2017 at 01:57:31PM +0100, Rainer Orth wrote:
I just noticed that nothing has happened at all in a month, so anything
is better than the tests XPASSing on a number of targets.
So the patch is ok for mainline with sparc*-*-* added to th
he issue. I don't happen to
have one that old to just test on.
I am seeing this failure on arm and aarch64 bare-metal environment where newlib
are used.
This patch also XFAIL this testcase on newlib.
OK for trunk?
Regards,
Jiong
gcc/testsuite/
2017-03-10 Jiong Wang
* g++.dg/tls
On 15/02/17 15:45, Richard Earnshaw (lists) wrote:
On 18/01/17 17:10, Jiong Wang wrote:
NOTE, this approach however requires DWARF change as the original LR
is signed,
the binary needs new libgcc to make sure c++ eh works correctly.
Given this
acceleration already needs the user specify
On 18/01/17 17:10, Jiong Wang wrote:
aarch64 cross check OK with the following options enabled on all testcases.
-fstack-protector-all -mstack-protector-pauth
OK for trunk?
gcc/
2017-01-18 Jiong Wang
* config
On 06/02/17 15:26, Jan Hubicka wrote:
I think it is not a regression, just the testcase if fragile and depends on
outcome
of ifcombine. It seems it was updated several time in the past. I am not quite
sure what the test is testing.
They are tring to make sure optimal stack adjustment decision
On 02/02/17 13:31, Gerald Pfeifer wrote:
On Thu, 2 Feb 2017, Jiong Wang wrote:
This patch adds a short entry for the -march=armv8.3-a and
-msign-return-address= options in GCC 7 to the "AArch64" section.
Thanks, Jiong.
Index: gcc-7/ch
Hi all,
This patch adds a short entry for the -march=armv8.3-a and -msign-return-address= options
in GCC 7 to the "AArch64" section.
Eyeballed the result in Firefox.
Ok to commit?
Thanks,
Jiong
Index: gcc-7/changes.html
===
RCS f
On 24/01/17 18:05, Adhemerval Zanella wrote:
On 03/01/2017 13:13, Wilco Dijkstra wrote:
+ /* If function uses stacked arguments save the old stack value so morestack
+ can return it. */
+ reg11 = gen_rtx_REG (Pmode, R11_REGNUM);
+ if (cfun->machine->frame.saved_regs_size
+ || cfun
On 20/01/17 18:23, Jiong Wang wrote:
OK, the attached patch disable the building of pointer signing code in
libgcc
on ILP32 mode, except the macro bit RA_A_SIGNED_BIT is still defined as I
want to book this bit for ILP32 as LP64 in case we later enable ILP32
support.
All pauth builtins
make sure they strictly follow the C
prototype. I also borrow the type define in ARM backend
typedef unsigned _uw64 __attribute__((mode(__DI__)));
And this is need to type cast the salt value which is always DImode.
It passed my local ILP32 cross build.
OK for trunk?
gcc/
2017-01-20 Jiong Wa
On 20/01/17 11:15, Jiong Wang wrote:
On 20/01/17 03:39, Andrew Pinski wrote:
On Fri, Jan 6, 2017 at 3:47 AM, Jiong Wang
wrote:
On 11/11/16 18:22, Jiong Wang wrote:
As described in the cover letter, this patch implements return address
signing
for AArch64, it's controlled by th
the attached patch as obvious, once I finished a fresh
bootstrap, cross elf, cross linux.
Thanks.
libgcc/
2017-01-20 Jiong Wang
* config/aarch64/linux-unwind.h: Always include aarch64-unwind.h.
diff --git a/libgcc/config/aarch64/linux-unwind.h b/libgcc/config/aarch64/linux-
On 20/01/17 03:39, Andrew Pinski wrote:
On Fri, Jan 6, 2017 at 3:47 AM, Jiong Wang wrote:
On 11/11/16 18:22, Jiong Wang wrote:
As described in the cover letter, this patch implements return address
signing
for AArch64, it's controlled by the new option:
-msign-return-address=
On 20/01/17 10:11, Christophe Lyon wrote:
/tmp/8132498_6.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-dw2.c:
In function 'execute_cfa_program':
/tmp/8132498_6.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-dw2.c:1193:17:
error: 'DWARF_REGNUM_AARCH64_RA_STATE' undeclared (
On 20/01/17 08:41, Christophe Lyon wrote:
Hi Jiong,
On 19 January 2017 at 15:46, Jiong Wang wrote:
Thanks for the review.
On 19/01/17 14:18, Richard Earnshaw (lists) wrote:
diff --git a/libgcc/unwind-dw2.c b/libgcc/unwind-dw2.c
index
8085a42ace15d53f4cb0c6681717012d906a6d47
y inline it anyway, but it seems wrong for us to rely on that.
Thanks, fixed.
Does the updated patch looks OK to you know?
libgcc/
2017-01-19 Jiong Wang
* config/aarch64/aarch64-unwind.h: New file.
(DWARF_REGNUM_AARCH64_RA_STATE): Define.
(MD_POST_
libgcc,
otherwise
you can't utilize new pointer authentication features.
gcc/
2016-11-11 Jiong Wang
* config/aarch64/aarch64-opts.h (aarch64_stack_protector_type): New
enum.
(aarch64_layout_frame): Swap callees and locals when
-mstack-protector-dialect=
On 12/01/17 18:10, Jiong Wang wrote:
On 06/01/17 11:47, Jiong Wang wrote:
This is the update on libgcc unwinder support according to new DWARF proposal.
As Joseph commented, duplication of unwind-dw2.c is not encouraged in libgcc,
But from this patch, you can see there are a few places we need
On 17/01/17 13:57, Richard Earnshaw (lists) wrote:
On 16/01/17 14:29, Jiong Wang wrote:
I can see the reason for doing this is if you want to seperate the
interpretion
of GCC CFA reg-note and the final DWARF CFA operation. My
understanding is all
reg notes defined in gcc/reg-note.def
On 13/01/17 18:02, Jiong Wang wrote:
On 13/01/17 16:09, Richard Earnshaw (lists) wrote:
On 06/01/17 11:47, Jiong Wang wrote:
This patch is an update on DWARF generation for return address signing.
According to new proposal, we simply needs to generate
REG_CFA_WINDOW_SAVE
annotation.
gcc
On 13/01/17 16:09, Richard Earnshaw (lists) wrote:
On 06/01/17 11:47, Jiong Wang wrote:
This patch is an update on DWARF generation for return address signing.
According to new proposal, we simply needs to generate REG_CFA_WINDOW_SAVE
annotation.
gcc/
2017-01-06 Jiong Wang
On 13/01/17 16:04, James Greenhalgh wrote:
On Fri, Jan 06, 2017 at 11:47:07AM +, Jiong Wang wrote:
On 11/11/16 18:22, Jiong Wang wrote:
gcc/
2017-01-06 Jiong Wang
* config/aarch64/aarch64-opts.h (aarch64_function_type): New enum.
* config/aarch64/aarch64-protos.h
On 06/01/17 11:47, Jiong Wang wrote:
This is the update on libgcc unwinder support according to new DWARF
proposal.
As Joseph commented, duplication of unwind-dw2.c is not encouraged in
libgcc,
But from this patch, you can see there are a few places we need to
modify for
AArch64 in unwind
On 11/11/16 18:22, Jiong Wang wrote:
We need customized EH unwinder support for AArch64 DWARF operations introduced
earlier in this patchset, these changes mostly need to be done in the generic
file unwind-dw2.c.
There are two ways of introducing these AArch64 support:
* Introducing a few
On 11/11/16 18:22, Jiong Wang wrote:
This patch implements a few ARMv8.3-A new builtins for pointer sign and
authentication instructions.
Currently, these builtins are supposed to be used by libgcc EH unwinder
only. They are not public interface to external user.
OK to install?
gcc/
2016-11
On 11/11/16 18:22, Jiong Wang wrote:
This patch add AArch64 specific runtime EH unwinding support for
DW_OP_AARCH64_pauth, DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_deref.
The semantics of them are described at the specification in patch [1/9].
The support includes:
* Parsing these
On 11/11/16 18:22, Jiong Wang wrote:
This patch generate DWARF description for pointer authentication. DWARF value
expression is used to describe the authentication action.
Please see the cover letter and AArch64 DWARF specification for the semantics
of AArch64 DWARF operations.
When
On 11/11/16 18:22, Jiong Wang wrote:
As described in the cover letter, this patch implements return address signing
for AArch64, it's controlled by the new option:
-msign-return-address=[none | non-leaf | all]
"none" means don't do return address signing at all on any
On 11/11/16 18:22, Jiong Wang wrote:
This patch add command line support for ARMv8.3-A through new architecture:
-march=armv8.3-a
ARMv8.3-A implies all default features of ARMv8.2-A and meanwhile it includes
the new pointer authentication extension.
gcc/
2016-11-08 Jiong Wang
On 28/12/16 19:54, Cary Coutant wrote:
OK on this proposal and to install this patch to gcc trunk?
Hi GDB, Binutils maintainer:
OK on this proposal and install this patch to binutils-gdb master?
include/
2016-11-29 Richard Earnshaw
Jiong Wang
* dwarf2.def
Jiong Wang writes:
> Jiong Wang writes:
>
>> Jiong Wang writes:
>>
>>> On 16/11/16 14:02, Jakub Jelinek wrote:
>>>> On Wed, Nov 16, 2016 at 02:54:56PM +0100, Mark Wielaard wrote:
>>>>> On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
Jiong Wang writes:
> Jiong Wang writes:
>
>> On 16/11/16 14:02, Jakub Jelinek wrote:
>>> On Wed, Nov 16, 2016 at 02:54:56PM +0100, Mark Wielaard wrote:
>>>> On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
>>>>>
Jiong Wang writes:
> On 16/11/16 14:02, Jakub Jelinek wrote:
>> On Wed, Nov 16, 2016 at 02:54:56PM +0100, Mark Wielaard wrote:
>>> On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
>>>> The two operations DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_der
:54:56PM +0100, Mark Wielaard wrote:
On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
The two operations DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_deref were
designed as shortcut operations when LR is signed with A key and using
function's CFA as salt. This is the default beha
On 16/11/16 14:02, Jakub Jelinek wrote:
On Wed, Nov 16, 2016 at 02:54:56PM +0100, Mark Wielaard wrote:
On Wed, 2016-11-16 at 10:00 +, Jiong Wang wrote:
The two operations DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_deref were
designed as shortcut operations when LR is signed with A
gcc/
2016-11-11 Jiong Wang
* function.c (expand_function_end): Guard stack_protect_epilogue
with
ENABLE_DEFAULT_SSP_RUNTIME.
* cfgexpand.c (pass_expand::execute): Likewise guard for
stack_protect_prologue.
* defaults.h (ENABLE_DEFAULT_SSP_RUNTIME): New
On 15/11/16 19:25, Richard Earnshaw (lists) wrote:
On 15/11/16 16:48, Jiong Wang wrote:
On 15/11/16 16:18, Jakub Jelinek wrote:
I know nothing about the aarch64 return address signing, would all 3
or say
2 usually appear together without any separate pc advance, or are they
all
going to appear
On 15/11/16 16:18, Jakub Jelinek wrote:
On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote:
Takes one signed LEB128 offset and retrieves 8-byte contents from the address
calculated by CFA plus this offset, the contents then authenticated as per A
key for instruction pointer
On 15/11/16 16:18, Jakub Jelinek wrote:
On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote:
Takes one signed LEB128 offset and retrieves 8-byte contents from the address
calculated by CFA plus this offset, the contents then authenticated as per A
key for instruction pointer
On 11/11/16 19:38, Jakub Jelinek wrote:
On Fri, Nov 11, 2016 at 06:21:48PM +, Jiong Wang wrote:
This patch introduces three AARCH64 private DWARF operations in vendor extension
space.
DW_OP_AARCH64_pauth 0xea
===
Takes one unsigned LEB 128 Pointer Authentication Description. Bits [3:0
On 11/11/16 22:12, Joseph Myers wrote:
On Fri, 11 Nov 2016, Jiong Wang wrote:
There are two ways of introducing these AArch64 support:
* Introducing a few target macros so we can customize functions like
uw_init_context, uw_install_context etc.
* Use target private unwind-dw2
ation be disabled.
How does this looks to you?
Thanks.
gcc/
2016-11-11 Jiong Wang
* function.c (expand_function_end): Guard stack_protect_epilogue with
ENABLE_DEFAULT_SSP_RUNTIME.
* cfgexpand.c (pass_expand::execute): Likewise guard for
stack_protect_prolo
have install new libgcc,
otherwise
you can't utilize new pointer authentication features.
gcc/
2016-11-11 Jiong Wang
* config/aarch64/aarch64-opts.h (aarch64_stack_protector_type): New
enum.
(aarch64_layout_frame): Swap callees and locals when
when the execution flow
continues at _Unwind_RaiseException's epilogue, the authentication still
works correctly.
OK for trunk?
libgcc/
2016-11-11 Jiong Wang
* config/aarch64/unwind-aarch64.c (RA_SIGN_BIT): New flag to indicate
one frame is return address s
/
2016-11-11 Jiong Wang
* config.host (aarch64*-*-elf, aarch64*-*-rtems*, aarch64*-*-linux*):
Include new AArch64 EH makefile.
* config/aarch64/t-eh-aarch64: New EH makefile.
* config/aarch64/unwind-aarch64.c: New EH unwinder implementation,
copied from unwind
This patch implements a few ARMv8.3-A new builtins for pointer sign and
authentication instructions.
Currently, these builtins are supposed to be used by libgcc EH unwinder
only. They are not public interface to external user.
OK to install?
gcc/
2016-11-11 Jiong Wang
* config
, -msign-return-address will introduce +24%
.debug_frame size increase when signing all functions and using compact
description, and about +45% .debug_frame size increase if using general
description.
gcc/
2016-11-11 Jiong Wang
* config/aarch64/aarch64.h (aarch64_pauth_action_type): New
are "a_key" for A key and "b_key" for B
key, and this option are supported by function target attribute and LTO will
hopefully just work.
gcc/
2016-11-09 Jiong Wang
* config/aarch64/aarch64-opts.h (aarch64_pauth_key_index): New enum.
(aarch64_function_type): N
This patch add command line support for ARMv8.3-A through new architecture:
-march=armv8.3-a
ARMv8.3-A implies all default features of ARMv8.2-A and meanwhile it includes
the new pointer authentication extension.
gcc/
2016-11-08 Jiong Wang
* config/aarch64/aarch64-arches.def: New
utils/LLVM scope, I only see one overlap between
DW_OP_GNU_push_tls_address and and DW_OP_HP_unknown, and DW_OP_HP_unknown seems
not used.
So I added the support in GCC generic code directly instead of introducing
target hook.
Is this OK to install?
gcc/
2016-11-11 Jiong Wang
* dwarf2
include/
2016-11-09 Richard Earnshaw
Jiong Wang
* dwarf2.def (DW_OP_AARCH64_pauth): Reserve the number 0xea.
(DW_OP_AARCH64_paciasp): Reserve the number 0xeb.
(Dw_OP_AARCH64_paciasp_deref): Reserve the number 0xec.
diff --git a/include/dwarf2.
flow protect on risky functions
---
sign LR+ 1.82% + 2.18% LR protect on All
Please review this patchset.
Thanks.
Jiong Wang (9):
[RFC] Reserve three DW_OP number in vendor extension space
Encoding supp
On 07/11/16 17:04, Bernd Schmidt wrote:
On 11/03/2016 03:00 PM, Eric Botcazou wrote:
FWIW here's a more complete version of my patch which I'm currently
testing. Let me know if you think it's at least a good enough
intermediate step to be installed.
It is, thanks.
Testing showed the same i
On 03/11/16 13:01, Bernd Schmidt wrote:
Index: gcc/emit-rtl.c
===
--- gcc/emit-rtl.c (revision 241233)
+++ gcc/emit-rtl.c (working copy)
@@ -6169,17 +6169,18 @@ emit_copy_of_insn_after (rtx_insn *insn,
which may be
On 03/11/16 12:06, Eric Botcazou wrote:
What's your decision on this?
I think that we ought to standardize on a single order for note copying in the
RTL middle-end and the best way to enforce it is to have a single primitive in
rtlanal.c, with an optional filtering. Bernd's patch is a step
On 02/11/16 13:42, Jakub Jelinek wrote:
On Wed, Nov 02, 2016 at 01:26:48PM +, Jiong Wang wrote:
-/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */
+/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note.
*/
Too long line.
Hmm, it
xpression note. My worry of conflict
makes no sense.
I updated the patch to put DWARF operation in to UNSPEC number field.
x86-64 bootstrap OK, no regression on gcc/g++.
Please review.
Thanks.
gcc/
2016-11-02 Jiong Wang
* reg-notes.def (CFA_VAL_EXPRESSION): New entry.
On 01/11/16 16:48, Jason Merrill wrote:
On Tue, Nov 1, 2016 at 11:59 AM, Jiong Wang wrote:
On 01/11/16 15:24, Jason Merrill wrote:
On Tue, Nov 1, 2016 at 11:12 AM, Jiong Wang wrote:
On 31/10/16 19:50, Jason Merrill wrote:
On 10/21/2016 04:30 AM, Jiong Wang wrote:
All DW_OP_* of the
On 01/11/16 15:24, Jason Merrill wrote:
On Tue, Nov 1, 2016 at 11:12 AM, Jiong Wang wrote:
On 31/10/16 19:50, Jason Merrill wrote:
On 10/21/2016 04:30 AM, Jiong Wang wrote:
All DW_OP_* of the expression are grouped together inside the PARALLEL,
and those operations which don't hav
On 31/10/16 19:50, Jason Merrill wrote:
On 10/21/2016 04:30 AM, Jiong Wang wrote:
All DW_OP_* of the expression are grouped together inside the PARALLEL,
and those operations which don't have RTL mapping are wrapped by
UNSPEC. The parsing algorithm is simply something like:
foreach
On 31/10/16 12:10, Kyrill Tkachov wrote:
Ping.
Thanks,
Kyrill
On 24/10/16 12:30, Kyrill Tkachov wrote:
Ping.
https://gcc.gnu.org/ml/gcc-patches/2016-10/msg00839.html
Thanks,
Kyrill
On 12/10/16 11:23, Kyrill Tkachov wrote:
Hi all,
I'm looking at the aarch64 prologue and epilogue generation
On 21/10/16 13:30, Bernd Schmidt wrote:
On 10/21/2016 02:04 PM, Jiong Wang wrote:
+ /* Locate the end of existing REG_NOTES in NEW_RTX. */
+ rtx *ptail = ®_NOTES (new_rtx);
+ while (*ptail != NULL_RTX)
+ptail = &XEXP (*ptail, 1);
I was thinking along the lines of something like
On 21/10/16 09:30, Jiong Wang wrote:
Currently, GCC only support DW_CFA_expression in dwarf module, this patch
extend the support to DW_CFA_val_expression which share the same code
mostly the same code with DW_CFA_expression.
Meanwhile the existed dwarf expression parser only allows expressions
On 24/10/16 16:22, Jeff Law wrote:
On 10/20/2016 01:46 PM, Jiong Wang wrote:
2016-10-20 19:50 GMT+01:00 Jeff Law :
On 10/20/2016 09:28 AM, Jiong Wang wrote:
The current code suppose targetm.stack_protect_fail always generate
something.
But in case one target start to generate NULL_TREE
0-21 Bernd Schmidt
Jiong Wang
gcc/
PR middle-end/78016
* emit-rtl.c (emit_copy_of_insn_after): Copy REG_NOTES in order instead
of in reverse order.
* sel-sched-ir.c (create_copy_of_insn_rtx): Likewise.
diff --git a/gcc/emit-rtl.c b/g
On 21/10/16 08:43, Eric Botcazou wrote:
That's also overcomplicated.
Yes, I agree that's too heavy.
rtx *ptail = ®_NOTES (to_insn);
while (*ptail != NULL_RTX)
ptail = &XEXP (*ptail, 1);
Thanks very much Bernd, yes, this is better. And through manipulating
pointer directly, those bidire
elem, 0, 0));
oprnd1 = INTVAL (XVECEXP (elem, 0, 1));
oprnd2 = INTVAL (XVECEXP (elem, 0, 2));
}
else
call standard RTL parser.
Any comments on the approach?
Thanks.
gcc/
2016-10-20 Jiong Wang
* reg-notes.def (CFA_VAL_EXPRESSION): New entry.
* d
2016-10-20 19:50 GMT+01:00 Jeff Law :
>
> On 10/20/2016 09:28 AM, Jiong Wang wrote:
>>
>> The current code suppose targetm.stack_protect_fail always generate
>> something.
>> But in case one target start to generate NULL_TREE, there will be ICE.
>> This
>>
The current code suppose targetm.stack_protect_fail always generate something.
But in case one target start to generate NULL_TREE, there will be ICE. This
patch adds a simple sanity check to only call expand if it's not NULL_TREE.
OK for trunk?
gcc/
2016-10-20 Jiong
are not
changed during insn copy. Redundant code in emit-rtl.c and sel-sched-ir.c are
deleted also.
x86_64/aarch64 bootstrap OK. c/c++ regression OK.
OK for trunk?
gcc/
2016-10-20 Jiong Wang
PR middle-end/78016
* lists.c (alloc_INSN_LIST_bidirection): New function. The
Hi Adhemerval,
On 06/10/16 22:54, Adhemerval Zanella wrote:
+ bool split_stack_arg_pointer_used = split_stack_arg_pointer_used_p ();
if (flag_stack_usage_info)
current_function_static_stack_size = frame_size;
@@ -3220,6 +3264,10 @@ aarch64_expand_prologue (void)
aarch64_em
On 27/09/16 17:03, Jiong Wang wrote:
>
> Now as ARM patches have gone in around r240427, I have done a quick
confirmation
> on the status of these four pending testsuite patches:
>
> https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00337.html
> https://gcc.gnu.org/ml/g
On 25/07/16 12:26, James Greenhalgh wrote:
On Thu, Jul 07, 2016 at 05:12:48PM +0100, Jiong Wang wrote:
Hello,
As a follow up of
https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01240.html,
This patch set adds ARMv8.2-A FP16 scalar and vector intrinsics support,
gcc middle-end will also be aware
0551.
gcc/testsuite/
2016-09-27 Jiong Wang
* lib/target-supports.exp
(check_effective_target_arm_v8_2a_fp16_scalar_hw): Delete redundant
word
in function comment.
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3d11e2
Wilco Dijkstra writes:
> Ping
>
> I noticed it would still be a good idea to add an extra barrier in the epilog
> as the
> scheduler doesn't appear to handle aliases of frame accesses properly.
>
> This patch simplifies the handling of the EH return value. We force the use
> of the
> frame poi
Adhemerval Zanella writes:
> On 08/08/2016 07:58, Jiong Wang wrote:
>>
>> Adhemerval Zanella writes:
>>
>
> Below it the last iteration patch, however I now seeing some similar issue
> s390 hit when building libgo:
>
> ../../../gcc-git/libgo/go/syscall/socke
Jiong Wang writes:
> Andrew Pinski writes:
>
>> On Mon, Jul 27, 2015 at 3:36 AM, James Greenhalgh
>> wrote:
>>> On Mon, Jul 27, 2015 at 10:52:58AM +0100, pins...@gmail.com wrote:
>>>> > On Jul 27, 2015, at 2:26 AM, Jiong Wang wrote:
>>>>
Adhemerval Zanella writes:
>> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
>> index e56398a..2cf239f 100644
>> --- a/gcc/config/aarch64/aarch64.c
>> +++ b/gcc/config/aarch64/aarch64.c
>> @@ -3227,6 +3227,34 @@ aarch64_expand_prologue (void)
>>RTX_FRAME_RELATED_
Andrew Pinski writes:
> On Mon, Jul 27, 2015 at 3:36 AM, James Greenhalgh
> wrote:
>> On Mon, Jul 27, 2015 at 10:52:58AM +0100, pins...@gmail.com wrote:
>>> > On Jul 27, 2015, at 2:26 AM, Jiong Wang wrote:
>>> >
>>> > Andrew Pinski writes:
>
Jiong Wang writes:
> On 07/07/16 10:34, James Greenhalgh wrote:
>>
>> To make backporting easier, could you please write a very simple
>> standalone test that exposes this bug, and submit this patch with just
>> that simple test? I've already OKed the functiona
On 21/07/16 11:08, Richard Earnshaw (lists) wrote:
On 20/07/16 16:02, Jiong Wang wrote:
Richard,
Thanks for the review, yes, I believe using aarch64_add_constant is
unconditionally
safe here. Because we have generated a stack tie to clobber the whole
memory thus
prevent any instruction
On 07/07/16 17:17, Jiong Wang wrote:
This patch add ARMv8.2-A FP16 two operands scalar intrinsics.
The updated patch resolve the conflict with
https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00309.html
The change is to let aarch64_emit_approx_div return false for HFmode.
gcc/
2016-07-20
On 07/07/16 17:17, Jiong Wang wrote:
This patch add ARMv8.2-A FP16 one operand scalar intrinsics
Scalar intrinsics are kept in arm_fp16.h instead of arm_neon.h.
The updated patch resolve the conflict with
https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00308.html
The change is to let
On 07/07/16 17:15, Jiong Wang wrote:
This patch add ARMv8.2-A FP16 two operands vector intrinsics.
The updated patch resolve the conflict with
https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00309.html
The change is to let aarch64_emit_approx_div return false for
V4HFmode and V8HFmode.
gcc
On 07/07/16 17:14, Jiong Wang wrote:
This patch add ARMv8.2-A FP16 one operand vector intrinsics.
We introduced new mode iterators to cover HF modes, qualified patterns
which was using old mode iterators are switched to new ones.
We can't simply extend old iterator like VDQF to conver HF
On 20/07/16 15:18, Richard Earnshaw (lists) wrote:
On 20/07/16 14:03, Jiong Wang wrote:
Those stack adjustment sequences inside aarch64_expand_prologue/epilogue
are doing exactly what's aarch64_add_constant offered, except they also
need to be aware of dwarf generation.
This patch
ch as aarch64_add_constant has better utilization of scratch register.
OK for trunk?
gcc/
2016-07-20 Jiong Wang
* config/aarch64/aarch64.c (aarch64_add_constant): Mark
instruction as frame related when it is. Generate CFA
annotation when it's
#x27;t do this if it fit into single move instruction, in which case
move the immedaite to scratch register firstly, then generate one
addition to add the scratch register to the destination register.
* Otherwise invoke general constant build function.
OK for trunk?
gcc/
20
ll the old
aarch64_build_constant.
OK for trunk?
gcc/
2016-07-20 Jiong Wang
* config/aarch64/aarch64.c (aarch64_add_constant): New
parameter "mode". Use aarch64_internal_mov_immediate
instead of aarch64_build_constant.
(aarch64_build_cons
On 07/07/16 10:34, James Greenhalgh wrote:
To make backporting easier, could you please write a very simple
standalone test that exposes this bug, and submit this patch with just
that simple test? I've already OKed the functional part of this patch, and
I'm happy to pre-approve a simple testcase
This patch add ARMv8.2-A FP16 three operands vector intrinsics.
Three operands intrinsics only contain fma and fms.
2016-07-07 Jiong Wang
gcc/
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64-simd.md (fma4): Extend to HF modes
This patch add ARMv8.2-A FP16 one operand scalar intrinsics
Scalar intrinsics are kept in arm_fp16.h instead of arm_neon.h.
gcc/
2016-07-07 Jiong Wang
* config.gcc (aarch64*-*-*): Install arm_fp16.h.
* config/aarch64/aarch64-builtins.c (hi_UP): New.
* config/aarch64
intrinsics with vdup intrinsics
2016-07-07 Jiong Wang
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_mulx_elt_to_64v2df):
Rename to
"*aarch64_mulx_elt_from_dup".
(*aarch64_mul3_elt): Update schedule type.
(*aarch64_mul3_elt_from_dup)
VDQF are with new FP16 support, thus we
introduced new, temperary iterators, and only apply new iterators on
those patterns which do have FP16 supports.
gcc/
2016-07-07 Jiong Wang
* config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New.
* config/aarch64/aarch64-simd-builtin
This patch add ARMv8.2-A FP16 two operands vector intrinsics.
gcc/
2016-07-07 Jiong Wang
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64-simd.md
(aarch64_rsqrts): Extend to HF modes.
(fabd3): Likewise.
(3): Likewise
1 - 100 of 464 matches
Mail list logo
