Re: [PATCH v2] RISC-V: Add autovec FP unary operations.

Hi Robin, Looks good to me except for note that this seems to depend on a new function: emit_vlmax_fp_insn which appears to be part of your autovec FP binary operation. So that patch would need to be merged first from what I can see. On 6/15/23 11:12, Robin Dapp via Gcc-patches wrote: Hi,

Re: [PATCH v2] RISC-V: Add autovec FP binary operations.

Robin, Why do we need '-ffast-math' with the tests? On 6/15/23 11:10, Robin Dapp via Gcc-patches wrote: Hi, changes from V1: - Add VF_AUTO iterator and use it. - Ensured we don't ICE with -march=rv64gcv_zfhmin. this implements the floating-point autovec expanders for binary operations: vf

Re: [PATCH v6 0/9] RISC-V: autovec: Add autovec support

in JuZhe’s patch set into this patch set? Michael Collison 於 2023年5月5日 週五，23:47寫道： This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation

[PATCH v6 6/9] RISC-V:autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

[PATCH v6 9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv.

From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/l

[PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect

[PATCH v6 8/9] RISC-V:autovec: Add autovectorization tests for binary integer

2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64.

[PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. (riscv_get_mask_mode

[PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): New function. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto

[PATCH v6 2/9] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH v6 5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store

2023-04-25 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector.md: Remove

[PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_vector_preferred_simd_mode): New. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto

[PATCH v6 0/9] RISC-V: autovec: Add autovec support

ener - Used RVV_VUNDEF macro to fix failing patterns Changes in v2 - Updated ChangeLog entry to include RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Kevin Lee (1): RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv

Re: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions

HI Kito, I see there have been many comments on the "riscv_vector_preferred_simd_mode" hook, is there an updated version? On 5/3/23 06:53, Kito Cheng wrote: @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* Implement TARGET_VECTORIZE_PRE

Re: [PATCH v4 05/10] RISC-V: autovec: Add autovectorization patterns for binary integer operations

Hi Robin and Juzhe, Just took a look and I like the approach. On 4/26/23 19:43, juzhe.zhong wrote: Yeah，Robin stuff is what I want and is making perfect sense for me. Replied Message FromRobin Dapp Date04/27/2023 02:15 To juzhe.zh...@rivai.ai

[PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE

[PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect

[PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv.

From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.

[PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): New function. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto

[PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv.

From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc index 8daf7bd7dd3..df393ba723

[PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer

2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64.

[PATCH v5 00/10] RISC-V: autovec: Add autovec support

contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Kevin Lee (2): This patch adds a guard for VNx1 vectors that are present in ports like riscv. This patch supports 8 bit auto-vectorization in riscv. Michael Collison (8): RISC-V: Add new predicates a

[PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

[PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store

2023-04-25 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector.md: Remove

[PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_vector_preferred_simd_mode): New. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto

Re: [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations

Hi Kito, I will remove the unused UNSPECs, thank you for finding them. I removed the include of "vector-iterators.md" because "riscv.md" already includes it and I was receiving multiple definition errors. On 4/18/23 21:19, Kito Cheng wrote: diff --git a/gcc/config/riscv/vector-iterators.md

Re: [PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

ener <mailto:richard.guent...@gmail.com>; Jeff Law <mailto:jeffreya...@gmail.com>; Palmer Dabbelt <mailto:pal...@dabbelt.com> *CC:* Michael Collison <mailto:colli...@rivosinc.com>; gcc-patches <mailto:gcc-patches@gcc.gnu.org>; 钟居哲 <mailto:juzhe.zh...

Re: [PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv.

:40 AM Michael Collison wrote: From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data

[PATCH v4 10/10] This patch supports 8 bit auto-vectorization in riscv.

From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.

[PATCH v4 08/10] RISC-V:autovec: Add autovectorization tests for binary integer

2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64.

[PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect

[PATCH v4 06/10] RISC-V:autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

[PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv.

From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc index 8daf7bd7dd3..df393ba723

[PATCH v4 03/10] RISC-V:autovec: Add auto-vectorization support functions

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_classify_vlmul_field): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto

[PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector

[PATCH v4 04/10] RISC-V:autovec: Add target vectorization hooks

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_option_override): Set riscv_vectorization_factor. (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement

[PATCH v4 01/10] RISC-V: Add new predicates and function prototypes

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto

[PATCH v4 00/10] RISC-V: Add autovec support

he code Kevin Lee (2): This patch adds a guard for VNx1 vectors that are present in ports like riscv. This patch supports 8 bit auto-vectorization in riscv. Michael Collison (8): RISC-V: Add new predicates and function prototypes RISC-V: autovec: Export policy functions to global scope

[PATCH v4 02/10] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH] vect: Verify that GET_MODE_NUNITS is greater than one.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is greater than one. --- gcc/tree-vect-slp.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc

[PATCH] vect: Verify that GET_MODE_NUNITS is power-of-2

Michael Collison * poly-int.h (exact_div_p): New function to verify that argument is a power of 2 poly_int. * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a power of 2. --- gcc/poly-int.h | 17 + gcc/tree

[PATCH v2] vect: Check that vector factor is a compile-time constant

2023-03-05 Michael Collison * tree-vect-loop-manip.cc (vect_do_peeling): Use result of constant_lower_bound instead of vf in case vf is not a compile time constant. --- gcc/tree-vect-loop-manip.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc

[PATCH v3 6/6] RISC-V: autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

[PATCH v3 5/6] RISC-V: autovec: Add autovectorization patterns for add & sub

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector

[PATCH v3 4/6] RISC-V: autovec: Add target vectorization hooks

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_option_override): Set riscv_vectorization_factor. (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement

[PATCH v3 2/6] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH v3 3/6] RISC-V: autovec: Add auto-vectorization support functions

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_classify_vlmul_field): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto

[PATCH v3 0/6] RISC-V: autovec: Add auto-vectorization support

de RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Michael Collison (6): RISC-V: Add new predicates and function prototypes RISC-V: autovec: Export policy functions to global scope RISC-V:autovec: Add auto-vectorization support functions

[PATCH v3 1/6] RISC-V: autovec: Add new predicates and function prototypes

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto

Re: [PATCH v2 00/07] RISC-V: autovec: Add auto-vectorization support

Thanks for the feedback, will try that next time. Michael Collison > On Mar 5, 2023, at 11:06 PM, Xi Ruoyao wrote: > > On Sun, 2023-03-05 at 22:13 -0500, Michael Collison wrote: > > /* snip */ > >> - Fixed ChangeLog email formatting > > Unfortunately it&#

[PATCH v2 07/07] RISC-V: autovec: Add autovectorization patterns for add & sub

This patch adds tests for autovectorization of integer add and subtract. gcc/testsuite/ChangeLog: 2023-03-02  Michael Collison                Vineet Gupta                 * gcc.target/riscv/rvv/autovec: New directory            for autovectorization tests

[PATCH V2 06/07] RISC-V: autovec: Add autovectorization patterns for add & sub

This patch adds patterns that provide basic autovectorization support for integer adds and subtracts. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong                * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include

[PATCH v2 05/07] RISC-V: autovec: Add tuning and target vectorization hooks

This patch adds support for registering target hooks for basic autovectorization support as well as basic tuning information for the vector extension. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv/riscv-cores.def (RISCV_TUNE

[PATCH v2 04/07] RISC-V: autovec: Add auto-vectorization support functions

This patch adds support for functions used in implementing various portions of autovectorization support. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv/riscv-v.cc (riscv_classify_vlmul_field):            New function

[PATCH v2 03/07] RISC-V: autovec: Add vector cost model

This patches adds two new files to support the vector cost model and modifies the Makefile fragment to build the cost model c++ file. Due to the large size this patch is provided as an attachment. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong

[PATCH v2 02/07] RISC-V: autovec: Export policy functions to global scope

This patch adds foundational support by making two functions that handle predication policies visibly globally. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred

[PATCH v2 01/07] RISC-V: autovec: Add new predicates and function prototypes

This patch adds foundational support in the form of: 1. New predicates 2. New function prototypes 3. Exporting emit_vlmax_vsetvl to global scope 4. Add a new command line option -mriscv_vector_lmu 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv

[PATCH v2 00/07] RISC-V: autovec: Add auto-vectorization support

This series of patches adds foundational support for RISC-V autovectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization pat

[PATCH 07/07] RISC-V: Add auto-vectorization support

This patch adds tests for autovectorization of integer add and subtract. gcc/testsuite/ChangeLog:     * gcc.target/riscv/rvv/autovec: New directory     for autovectorization tests.     * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New     test to verify code generation of vector add on rv32.  

[PATCH 06/07] RISC-V: Add auto-vectorization support

ription for RISC-V 'V' Extension for GNU compiler. +;; Copyright (C) 2022-2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd. +;; Contributed by Michael Collison (colli...@rivosinc.com, Rivos Inc. + +;; This file is part of GCC

[PATCH 05/07] RISC-V: Add auto-vectorization support

This patch adds support for registering target hooks for basic autovectorization support as well as basic tuning information for the vector extension. gcc/ChangeLog:     * config/riscv/riscv-cores.def (RISCV_TUNE):     Add VECTOR_TUNE_INFO parameter and     * common/config/riscv/riscv-common.c

[PATCH 04/07] RISC-V: Add auto-vectorization support

This patch adds support for functions used in implementing various portions of autovectorization support. gcc/ChangeLog:     * config/riscv/riscv-v.cc (riscv_classify_vlmul_field):     New function.     (riscv_vector_preferred_simd_mode): Ditto.     (get_mask_policy_no_pred): Ditto.     (get_ta

[PATCH 03/07] RISC-V: Add auto-vectorization support

From: Michael Collison Date: Thu, 2 Mar 2023 12:27:36 -0500 Subject: [PATCH] Autovectorization patch set 2 --- gcc/config.gcc| 2 +- gcc/config/riscv/riscv-vector-cost.cc | 620 ++ gcc/config/riscv/riscv-vector-cost.h | 400 + gcc

[PATCH 02/07] RISC-V: Add auto-vectorization support

This patch adds foundational support by making two functions that handle predication policies visibly globally. gcc/ChangeLog:     * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):     Remove static declaration to to make externally visible.     (get_mask_policy_for_pred): Dit

[PATCH 01/07] RISC-V: Add auto-vectorization support

This patch adds foundational support in the form of: 1. New predicates 2. New function prototypes 3. Exporting emit_vlmax_vsetvl to global scope 4. Add a new command line option -mriscv_vector_lmul gcc/ChangeLog:     * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):     New externa

[PATCH 00/07] RISC-V: Add auto-vectorization support

This series of patches adds foundational support for RISC-V autovectorization. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization patterns th

Re: [PATCH] vect: Check that vector factor is a compile-time constant

able VF. It might be possible to trigger the problem on SVE too, with a sufficiently convoluted test case. (Haven't tried though.) Richard Biener writes: On Wed, Feb 22, 2023 at 12:03 AM Michael Collison wrote: While working on autovectorizing for the RISCV port I encountered an issue where vec

Re: [PATCH] vect: Check that vector factor is a compile-time constant

ation work is no more experimental than the intrinsics work which is still being merged. On 2/22/23 23:01, Jeff Law wrote: On 2/22/23 10:54, Michael Collison wrote: Juzhe, I disagree with this comment. There are many stakeholders for autovectorization and waiting until GCC 14 is not a viab

Re: [PATCH] vect: Check that vector factor is a compile-time constant

Juzhe, I disagree with this comment. There are many stakeholders for autovectorization and waiting until GCC 14 is not a viable solution for us as well as other stakeholders ready to begin work on autovectorization. As we discussed I have been moving forward with patches for autovectorizatio

Re: [PATCH] vect: Check that vector factor is a compile-time constant

Richard how would I check for a full masked main vector loop? On 2/22/23 03:20, Richard Biener wrote: On Wed, Feb 22, 2023 at 12:03 AM Michael Collison wrote: While working on autovectorizing for the RISCV port I encountered an issue where vect_do_peeling assumes that the vectorization factor

[PATCH] vect: Check that vector factor is a compile-time constant

While working on autovectorizing for the RISCV port I encountered an issue where vect_do_peeling assumes that the vectorization factor is a compile-time constant. The vectorization is not a compile-time constant on RISCV. Tested on RISCV and x86_64-linux-gnu. Okay? Michael gcc/     * tree-v

Re: [PATCH v2] match.pd: rewrite select to branchless expression

Richard, Can you submit this patch for me while I sort out git write access? On 11/18/22 07:57, Richard Biener wrote: On Fri, Nov 11, 2022 at 3:28 AM Michael Collison wrote: This patches transforms ((x & 0x1) == 0) ? y : z y -into (-(typeof(y))(x & 0x1) & z) y, where op i

Re: [PATCH v2] match.pd: rewrite select to branchless expression

: On Fri, 11 Nov 2022 at 07:58, Michael Collison wrote: This patches transforms ((x & 0x1) == 0) ? y : z y -into (-(typeof(y))(x & 0x1) & z) y, where op is a '^' or a '|'. It also transforms (cond (and (x , 0x1) != 0), (z op y), y ) into (-(and (x , 0x1)) &am

[PATCH v2] match.pd: rewrite select to branchless expression

rate branchless code for one of the functions in coremark. Bootstrapped and tested on x86 and RISC-V. Okay? Michael. 2022-11-10  Michael Collison      * match.pd ((x & 0x1) == 0) ? y : z y     -> (-(typeof(y))(x & 0x1) & z) y. 2022-11-10  Michael Collison     * gcc.dg/tree-s

Re: [PATCH] match.pd: rewrite select to branchless expression

    (op (bit_and (negate (convert:type (bit_and @0 { build_one_cst (type); }))) @2) @1 On 11/9/22 02:41, Richard Biener wrote: On Tue, Nov 8, 2022 at 9:02 PM Michael Collison wrote: This patches transforms (cond (and (x , 0x1) == 0), y, (z op y)) into (-(and (x , 0x1)) & z ) op y, wh

[PATCH] match.pd: rewrite select to branchless expression

rate branchless code for one of the functions in coremark. Bootstrapped and tested on x86 and RISC-V. Okay? Michael. 2022-11-08  Michael Collison      * match.pd ((cond (and (x , 0x1) == 0), y, (z op y) )     -> (-(and (x , 0x1)) & z ) op y) 2022-11-08  Michael Collison      * gcc

Re: [PATCH 1/4] Clean up of new format of -falign-FOO.

ET_THUMB ? 2 : 4; return align > min_insn_size ? align - min_insn_size : 0; } Which breaks with your current change. I think this needs to be modified to: 'align = 1 << label_to_alignment (label).levels[0].log' Regards, Michael Collison

[PING][PATCH][Aarch64] v2: Arithmetic overflow addv patterns [Patch 2/4]

Ping. Last patch here: https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00735.html

RE: [PATCH][Aarch64] v2: Arithmetic overflow subv patterns [Patch 3/4]

-31 Michael Collison Richard Henderson * config/aarch64/aarch64.md (subv4, usubv4): New patterns. (subti): Handle op1 zero. (subvti4, usub4ti4): New. (*sub3_compare1_imm): New. (sub3_carryinCV): New. (*sub3_carryinCV_z1_z2

RE: [PATCH][Aarch64] v2: Arithmetic overflow addv patterns [Patch 2/4]

Updated with Richard's style and mismatched mode comments. Okay for trunk? -Original Message- From: Richard Sandiford Sent: Monday, June 11, 2018 11:47 AM To: Michael Collison Cc: James Greenhalgh ; GCC Patches ; nd Subject: Re: [PATCH][Aarch64] v2: Arithmetic overflow addv pat

RE: [PATCH][Aarch64] v2: Arithmetic overflow subv patterns [Patch 3/4]

All requested changes made: - label_ref added as operand 3 - more descriptive variable names used Okay for trunk? -Original Message- From: James Greenhalgh Sent: Thursday, June 7, 2018 5:30 PM To: Michael Collison Cc: GCC Patches ; nd Subject: Re: [PATCH][Aarch64] v2: Arithmetic

RE: [PATCH][Aarch64] v2: Arithmetic overflow addv patterns [Patch 2/4]

All requested changes made: - label_ref added as operand 3 - more meaningful names given to variables Okay for trunk? -Original Message- From: James Greenhalgh Sent: Thursday, June 7, 2018 5:29 PM To: Michael Collison Cc: GCC Patches ; nd Subject: Re: [PATCH][Aarch64] v2: Arithmetic

RE: [PATCH][Aarch64] v2: Arithmetic overflow common functions [Patch 1/4]

x27; aarch64_gen_unlikely_cbranch'. Okay for trunk? -Original Message- From: James Greenhalgh Sent: Thursday, June 7, 2018 5:19 PM To: Michael Collison Cc: GCC Patches ; nd Subject: Re: [PATCH][Aarch64] v2: Arithmetic overflow common functions [Patch 1/4] On Wed, Jun 06, 2018 at 1

[PATCH][Aarch64] v2: Arithmetic overflow tests [Patch 4/4]

for patch here: https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html This patch contains new test cases to verify that the new overflow patterns are being utilized. Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk? 2018-05-31 Michael Collison Richard Henderson

[PATCH][Aarch64] v2: Arithmetic overflow subv patterns [Patch 3/4]

for patch here: https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html This patch contains new patterns for subv overflow patterns. Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk? 2018-05-31 Michael Collison Richard Henderson * config/aarch64/aarch64.md

[PATCH][Aarch64] v2: Arithmetic overflow addv patterns [Patch 2/4]

for patch here: https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html This patch contains new patterns for addv overflow patterns. Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk? 2018-05-31 Michael Collison Richard Henderson * config/aarch64/aarch64.md

[PATCH][Aarch64] v2: Arithmetic overflow common functions [Patch 1/4]

CC_Vmode is introduced. Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk? 2018-05-31 Michael Collison Richard Henderson * config/aarch64/aarch64-modes.def (CC_V): New. * config/aarch64/aarch64-protos.h (aarch64_add_128bit_scratch_regs): Declare (aarch64_subv_128bit_scratch_regs

[PATCH 2/2][Aarch64] Improve FP to int conversions

, s0 ret We can merge the float_truncate into the fix at the rtl level With -ffast-math enabled and -O2 we can now generate: f6: fcvtzs w0, d0 ret Bootstrapped and regression tested on aarch64-linux-gnu. Okay for trunk? 2018-05-15 Michael Collison

[PATCH 1/2][Aarch64] Improve FP to int conversions

one instruction at -O2 f7: fcvtzu x0, d0 ret Bootstrapped and regression tested on aarch64-linux-gnu. Okay for trunk? 2018-05-15 Michael Collison * config/aarch64/aarch64.md: (*fix_to_zero_extenddfdi2): New pattern. * gcc.target/aarch64

[Arm] GCC crash in cprop_hardreg when targeting v8-A Thumb

ict_it". This was causing illegal rtl to be generated for IT blocks which in turn caused an internal error. Bootstrapped and regression tested on arm-linux-gnueabihf. Okay for trunk? 2018-01-28 Michael Collison * config/arm/thumb2.md: (*thumb2_mov_negscc

RE: [PATCH 5/5][AArch64] fp16fml support

Okay will put on my to-do list for post GCC 8. -Original Message- From: James Greenhalgh [mailto:james.greenha...@arm.com] Sent: Wednesday, January 10, 2018 12:21 PM To: Michael Collison Cc: Richard Sandiford ; GCC Patches ; nd Subject: Re: [PATCH 5/5][AArch64] fp16fml support On Tue

RE: [PATCH 5/5][AArch64] fp16fml support

Patch updated per Richard's comments. Ok for trunk? -Original Message- From: Richard Sandiford [mailto:richard.sandif...@linaro.org] Sent: Thursday, January 4, 2018 8:02 AM To: Michael Collison Cc: GCC Patches ; nd Subject: Re: [PATCH 5/5][AArch64] fp16fml support Hi Michael,

RE: [PATCH 1/5][AArch64] Crypto command line split

conditional statement changed from TARGET_CRYPTO to TARGET_AES. -Original Message- From: James Greenhalgh [mailto:james.greenha...@arm.com] Sent: Tuesday, January 9, 2018 10:44 AM To: Michael Collison Cc: GCC Patches ; nd Subject: Re: [PATCH 1/5][AArch64] Crypto command line split On Wed

[PATCH 5/5][AArch64] fp16fml support

. Test cases were added to verify that the ACLE Intrinsics generate the appropriate FP16 multiply add/subtract assembly instructions. Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all instructions assembly correctly. Okay for trunk? 2017-11-10 Michael Collison

[PATCH 4/5][AArch64] Crypto sha512 and sha3

Intrinsics generate the appropriate SHA-512/SHA-3 assembly instructions. Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all instructions assembly correctly. Okay for trunk? 2017-11-10 Michael Collison * config/aarch64/aarch64-builtins.c

[PATCH 3/5][AArch64] Crypto SM4 Support

Intrinsics generate the appropriate SM3/SM4 assembly instructions. Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all instructions assembly correctly. Okay for trunk? 2017-11-10 Michael Collison * config/aarch64/aarch64-builtins.c

[PATCH 2/5][AArch64] Add v8.4 architecture

Hi all, This patch adds support for the Arm architecture v8.4. A new command line option, -march=armv8.4-a, is added as well as documentation. Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all instructions assembly correctly. 2017-11-10 Michael Collison

[PATCH 1/5][AArch64] Crypto command line split

verified all instructions assembly correctly. 2017-11-10 Michael Collison * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): (__ARM_FEATURE_AES): Define if TARGET_AES is true. (__ARM_FEATURE_SHA2): Define if TARGET_SHA2 is true. * config/aarch64

[PATCH 0/5][AArch64] ARMv8.4-A support

Hello, The ARMv8.4-A architecture builds on ARMv8.3-A and includes optional cryptographic extensions supporting SHA512, SHA3, SM3 and SM4. New FP16 multiply add/subtract instructions have been added that are mandatory in ARMv8.4-A and optional from ARMv8.2-A onward.  Although the new cryptogr

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