On Wed, Mar 02, 2022 at 06:47:39PM -0600, Segher Boessenkool wrote:
> Please use src instead of dest_lo. This always works, because you did
> the low-part move first.
That doesn't work in the case where src is a memory operation. Dest_lo is
guarantee to be a register, but src isn't.
--
On Wed, Mar 02, 2022 at 06:47:39PM -0600, Segher Boessenkool wrote:
> On Wed, Mar 02, 2022 at 03:54:29PM -0500, Michael Meissner wrote:
> > Optimize signed DImode -> TImode on power10.
>
> > On power10, GCC tries to optimize the signed conversion from DImode to
> > TImode by using the vextsd2q
Optimize signed DImode -> TImode on power10.
In comparison to the patch I submitted on February 25th, this patch changes the
comments based on feedback from Will Schmidt, and I added 2 test cases, to test
the conversion when the target registers are GPRs and when the target registers
are Altivec
Optimize signed DImode -> TImode on power10, PR target/104698.
On power10, GCC tries to optimize the signed conversion from DImode to
TImode by using the vextsd2q instruction. However to generate this
instruction, it would have to generate 3 direct moves (1 from the GPR
registers to the altivec
On Thu, Feb 24, 2022 at 08:07:28AM +0100, Robin Dapp wrote:
> Hi,
>
> > Robin's patch has the effct making rs6000_emit_int_cmove return false for
> > floating point comparisons, so I marked the bug as being a duplicate of PR
> > target/104335.
>
> Didn't I just return false for MODE_CC? This
On Thu, Feb 17, 2022 at 05:38:07PM -0600, Segher Boessenkool wrote:
> Hi!
>
> First, you need to adjust after Robin's patch, and retest.
Robin's patch has the effct making rs6000_emit_int_cmove return false for
floating point comparisons, so I marked the bug as being a duplicate of PR
Don't do int cmoves for IEEE comparisons, PR target/104256.
Protect int cmove from raising an assertion if it is trying to do an int
conditional move where the test involves floating point comparisons that
can't easily be reversed due to NaNs.
The code used to generate the condition, and
[PATCH, V3] Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__.
Define the sizes of the PowerPC specific types __float128 and __ibm128 if those
types are enabled.
This patch will define __SIZEOF_IBM128__ and __SIZEOF_FLOAT128__ if their
respective types are created in the compiler. Currently,
On Tue, Feb 15, 2022 at 04:05:11PM -0600, Segher Boessenkool wrote:
> On all older compilers these macros will not be defined, but the types
> often are. If you are willing to not support older compilers properly
> anyway, you could just *always* use the types, which will work with most
> very
On Tue, Feb 15, 2022 at 01:45:06PM -0600, Segher Boessenkool wrote:
> On Tue, Feb 15, 2022 at 12:49:41PM -0500, Michael Meissner wrote:
> > Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__.
> >
> > Define the sizes of the PowerPC specific types __float128 and __ibm128 if
> > those
> > types are
Define __SIZEOF_FLOAT128__ and __SIZEOF_IBM128__.
Define the sizes of the PowerPC specific types __float128 and __ibm128 if those
types are enabled.
I tested this on a little endian power9 system and there were no regressions.
Can I check this into the trunk, and after a burn-in period, can I
Ping patch for PR target/102059 to ignore implicit -mpower8-fusion that
prevents a function targeting power9 or power10 from inlining a function that
declared it needed power8 via attribute/pragma target.
While we likely should revist this in GCC 13, this patch is fairly minimal in
that it fixes
Ping patch to fix PR target/104253. This patch fixes using the wrong names for
conversions between __ibm128 and integer types if the long double default is
IEEE 128-bit.
| Date: Fri, 28 Jan 2022 22:47:06 -0500
| From: Michael Meissner
| Subject: [PATCH], PR 104253, Fix __ibm128 conversions on
On Wed, Feb 09, 2022 at 04:56:13PM +0800, Kewen.Lin wrote:
> Hi Michael,
>
> on 2022/2/9 上午11:27, Michael Meissner via Gcc-patches wrote:
> > Reset -mpower8-fusion for power9 inlining power8 functions, PR 102059.
> >
> > This patch is an attempt to make a much simpler
Reset -mpower8-fusion for power9 inlining power8 functions, PR 102059.
This patch is an attempt to make a much simpler patch to fix PR target/102059
than the previous patch.
It just fixes the issue that if a function is specifically declared as a power8
function, you can't inline in functions
Use system default for long double unless it is overridden.
If the user did not specify a default long double format when configuring
GCC, use the long double default from the host compiler.
I tested this on the following systems. There were no regressions:
* Big endian Linux power8
On Mon, Jan 31, 2022 at 12:52:28PM -0600, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Jan 31, 2022 at 01:49:03PM -0500, Michael Meissner wrote:
> > * config/rs6000/rs6000.cc (TARGET_IEEEQUAD_DEFAULT): If the
> > compiler used to build the current compiler defaults to IEEE
> > 128-bit
This patch is critical to be installed when distros start making the switch
from IBM 128-bit long double to IEEE 128-bit long double, so that users don't
have to explicitly set the floating point format.
Note because the patch was posted before the .c files were renamed to .cc, the
following
Use correct names for __ibm128 if long double is IEEE 128-bit.
If you are on a PowerPC system where the default long double is IEEE
128-bit, GCC will use the wrong names for some of the conversion functions
for the __ibm128 type.
What is happening is when the defult long double is IEEE 128-bit,
Ping patch.
https://gcc.gnu.org/pipermail/gcc-patches/2022-January/588292.html
| Date: Wed, 12 Jan 2022 13:04:19 -0500
| From: Michael Meissner
| Subject: [PATCH] Use system default for long double if not specified on
PowerPC.
| Message-ID:
I believe this patch will be very important when
Ping patch
https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587924.html
| Date: Fri, 7 Jan 2022 16:05:53 -0500
| From: Michael Meissner
| Subject: [PATCH] PR 103763, Fix fold-vec-splat-floatdouble on power10.
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA,
Mark XXSPLTIW/XXSPLTIDP as prefixed -- PR 104136
If you compile module_advect_em.F90 with -Ofast -mcpu=power10, one module
is large enough that we can't use a single conditional jump to span the
function. Instead, GCC has to reverse the condition, and do a conditional
jump around an
Use system default for long double if not specified on PowerPC.
If the user did not specify a default long double format, use the long double
default for the build compiler for the long double default. This patch will
allow compilers built on a distribution that has changed the 128-bit floating
On Wed, Jan 12, 2022 at 06:50:04PM +0100, Jakub Jelinek wrote:
> On Wed, Jan 12, 2022 at 12:46:16PM -0500, Michael Meissner via Gcc-patches
> wrote:
> > Allow other languages to change long double format on PowerPC.
> >
> > With Fortran adding support for changin
Allow other languages to change long double format on PowerPC.
With Fortran adding support for changing the long double format, this
patch removes the code that only allowed C/C++ to change the long double
format for GLIBC 2.32 and later without a warning.
I have bootstraped the compiler with
On Sat, Jan 08, 2022 at 02:15:14PM -0500, David Edelsohn wrote:
> On Sat, Jan 8, 2022 at 1:59 PM Michael Meissner
> wrote:
> >
> > On Sat, Jan 08, 2022 at 03:18:07PM +0100, Jakub Jelinek wrote:
> > > On Sat, Jan 08, 2022 at 03:13:10PM +0100, Thomas Koenig wrote:
> > > >
> > > > On 08.01.22
On Sat, Jan 08, 2022 at 03:18:07PM +0100, Jakub Jelinek wrote:
> On Sat, Jan 08, 2022 at 03:13:10PM +0100, Thomas Koenig wrote:
> >
> > On 08.01.22 15:02, Jakub Jelinek via Fortran wrote:
> > > Note, as for byteswapping, apparently it wasn't ever working right fox
> > > the IBM extended
Fix pr101384-1.c code generation test.
Add support for the compiler using XXSPLTIB reg,255 to load all 1's into a
register on power9 and above instead of using VSPLTI{B,H,W} reg,-1.
gcc/testsuite/
2022-01-07 Michael Meissner
PR testsuite/102935
*
Fix fold-vec-splat-floatdouble testsuite failure on power10
When I added support for generating XXSPLTIDP on December 15th, 2021, I
missed updating the fold-vec-splat-floatdouble.c test to add to the regex
for the instructions generated. This patch fixes that.
gcc/testsuite/
2022-01-07 Michael
On Tue, Jan 04, 2022 at 12:07:49PM +0100, Jakub Jelinek wrote:
> On Mon, Jan 03, 2022 at 11:43:57PM +0100, Thomas Koenig wrote:
> > > clearly there is still work to fix (but seems e.g. most of the lto tests
> > > are related to the gnu attributes stuff:( ).
> >
> > This is looking better than
On Tue, Jan 04, 2022 at 12:07:49PM +0100, Jakub Jelinek wrote:
> On Mon, Jan 03, 2022 at 11:43:57PM +0100, Thomas Koenig wrote:
> > > clearly there is still work to fix (but seems e.g. most of the lto tests
> > > are related to the gnu attributes stuff:( ).
> >
> > This is looking better than
On Tue, Jan 04, 2022 at 12:07:49PM +0100, Jakub Jelinek wrote:
> On Mon, Jan 03, 2022 at 11:43:57PM +0100, Thomas Koenig wrote:
> > > clearly there is still work to fix (but seems e.g. most of the lto tests
> > > are related to the gnu attributes stuff:( ).
> >
> > This is looking better than
On Mon, Jan 03, 2022 at 04:24:50PM +0100, Jakub Jelinek wrote:
> Hi!
>
> Testing found that we also need libquadmath to be built with
> -mno-gnu-attribute, otherwise -mabi=ieeelongdouble programs don't link.
>
> Ok for power-ieee128?
>
> 2022-01-03 Jakub Jelinek
>
> * configure.ac:
Ping patch.
| Date: Fri, 19 Nov 2021 09:57:49 -0500
| From: Michael Meissner
| Subject: [PATCH 3/3] Use absolute switch table addresses for zero cycle moves.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/585007.html
Note, I will on-line through December 20th. I will
Ping patch.
| Date: Fri, 19 Nov 2021 09:55:50 -0500
| From: Michael Meissner
| Subject: [PATCH 2/3] Set power10 fusion if -mtune=power10.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/585006.html
Note, I will be on-line through December 20th. I will be off-line
Ping patch.
| Date: Fri, 19 Nov 2021 09:53:14 -0500
| From: Michael Meissner
| Subject: [PATCH 1/3] Add power10 zero cycle moves for switches & indirect
jumps
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/585005.html
Note, I will on-line through December 20th. I will
Ping patch #2.
| Date: Fri, 5 Nov 2021 00:11:20 -0400
| From: Michael Meissner
| Subject: [PATCH 5/5] Add Power10 XXSPLTIDP for SFmode/DFmode constants.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583394.html
Note, I will be on-line through December 20th. I will be
Ping patch #2.
| Date: Fri, 5 Nov 2021 00:10:18 -0400
| From: Michael Meissner
| Subject: [PATCH 4/5] Add Power10 XXSPLTIDP for vector constants
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583393.html
Note, I will be on-line through December 20th. I will be off-line
Ping patch #2.
| Date: Fri, 5 Nov 2021 00:09:07 -0400
| From: Michael Meissner
| Subject: [PATCH 3/5] Add Power10 XXSPLTIW
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583392.html
Note, I will on-line through December 20th. I will be off-line after that
until
Ping patch #2.
| Date: Fri, 5 Nov 2021 00:07:05 -0400
| From: Michael Meissner
| Subject: [PATCH 2/5] Add Power10 XXSPLTI* and LXVKQ instructions (LXVKQ)
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583391.html
Note, I will on-line until December 20th, and then
Ping patch.
| Date: Fri, 5 Nov 2021 00:04:40 -0400
| From: Michael Meissner
| Subject: [PATCH 1/5] Add XXSPLTI* and LXVKQ instructions (new data structure
and function)
| Message-ID:
Note, I will on-line until December 20th, and then I won't be on-line until
January.
--
Michael Meissner,
On Mon, Nov 29, 2021 at 10:57:12AM -0600, Segher Boessenkool wrote:
> Why are there OPTION_MASKs for separate P10 fusion types here, as well as
> MASK_P10_FUSION?
Well going back in time, before we used rs6000_isa_flags, we used the default
flag word for MASK arguments. Unfortunately, the
On Mon, Nov 22, 2021 at 11:09:22AM -0500, David Edelsohn wrote:
> On Mon, Nov 22, 2021 at 10:58 AM Bill Schmidt wrote:
> And do the absolute addressing for switch tables changes work on AIX?
> I thought that Hao Chen only had done the work for PPC64 Linux ELF
> syntax with promises of future
On Mon, Nov 22, 2021 at 10:06:17AM -0600, Bill Schmidt wrote:
> Hi Mike,
>
> On 11/19/21 8:55 AM, Michael Meissner wrote:
> > Set power10 fusion if -mtune=power10.
> >
> > In doing the patch for zero cycle moves for switch statements and indirect
> > jumps, I noticed the fusion support is only
On Mon, Nov 22, 2021 at 10:36:13AM -0600, Bill Schmidt wrote:
> Hi Mike,
>
> Thanks for this patch!
> > --- a/gcc/config/rs6000/rs6000.md
> > +++ b/gcc/config/rs6000/rs6000.md
> > @@ -12988,15 +12988,34 @@ (define_expand "indirect_jump"
> > emit_jump_insn (gen_indirect_jump_nospec (Pmode,
se absolute switch table addresses for zero cycle moves.
This option enables using absolute addresses in switch tables if the
power10 zero cycle move tuning is turned on. The combination of using
absolute addresses in switch tables along with zero cycle moves seems to
give the best performance.
Set power10 fusion if -mtune=power10.
In doing the patch for zero cycle moves for switch statements and indirect
jumps, I noticed the fusion support is only done if -mcpu=power10. This option
enables power10 fusion if we use -mtune=power10.
I have built and run the testsuites on little endian
Add power10 zero cycle moves for switches.
Power10 will fuse adjacenet 'mtctr' and 'bctr' instructions to form zero
cycle moves. This code exploits this fusion opportunity.
I have built bootstrapped compilers with this patch on little endian power9 and
power10 systems with no regressions. Can
The next set of 3 patches add zero cycle move support to the Power10. Zero
cycle moves are where the move to LR/CTR/TAR register that is adjacent to the
jump to LR/CTR/TAR register can be fused together.
At the moment, these set of three patches add support for zero cycle moves for
indirect
Ping patch.
| Date: Fri, 5 Nov 2021 00:11:20 -0400
| Subject: [PATCH 5/5] Add Power10 XXSPLTIDP for SFmode/DFmode constants.
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Ping patch.
| Date: Fri, 5 Nov 2021 00:10:18 -0400
| Subject: [PATCH 4/5] Add Power10 XXSPLTIDP for vector constants
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Ping patch.
| Date: Fri, 5 Nov 2021 00:09:07 -0400
| Subject: [PATCH 3/5] Add Power10 XXSPLTIW
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Ping patch:
| Date: Fri, 5 Nov 2021 00:07:05 -0400
| Subject: [PATCH 2/5] Add Power10 XXSPLTI* and LXVKQ instructions (LXVKQ)
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Ping patch.
| Date: Fri, 5 Nov 2021 00:04:40 -0400
| Subject: [PATCH 1/5] Add XXSPLTI* and LXVKQ instructions (new data structure
and function)
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Fri, Nov 05, 2021 at 12:01:43PM -0500, will schmidt wrote:
> On Fri, 2021-11-05 at 00:04 -0400, Michael Meissner wrote:
> > Add new constant data structure.
> >
> > This patch provides the data structure and function to convert a
> > CONST_INT, CONST_DOUBLE, CONST_VECTOR, or VEC_DUPLICATE of a
On Fri, Nov 05, 2021 at 12:52:51PM -0500, will schmidt wrote:
> > diff --git a/gcc/config/rs6000/predicates.md
> > b/gcc/config/rs6000/predicates.md
> > index 956e42bc514..e0d1c718e9f 100644
> > --- a/gcc/config/rs6000/predicates.md
> > +++ b/gcc/config/rs6000/predicates.md
> > @@ -601,6 +601,14
I mentioned that I would start a build/check on a big endian power8 system in
the last set of patches. There were no regressions with this set of patches on
a big endian system, testing both 32-bit and 64-bit code generation.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
Generate XXSPLTIDP for scalars on power10.
This patch implements XXSPLTIDP support for SF, and DF scalar constants.
The previous patch added support for vector constants. This patch adds
the support for SFmode and DFmode scalar constants.
I added 2 new tests to test loading up SF and DF scalar
Generate XXSPLTIDP for vectors on power10.
This patch implements XXSPLTIDP support for all vector constants. The
XXSPLTIDP instruction is given a 32-bit immediate that is converted to a vector
of two DFmode constants. The immediate is in SFmode format, so only constants
that fit as SFmode
Generate XXSPLTIW on power10.
This patch adds support to automatically generate the ISA 3.1 XXSPLTIW
instruction for V8HImode, V4SImode, and V4SFmode vectors. It does this by
adding support for vector constants that can be used, and adding a
VEC_DUPLICATE pattern to generate the actual XXSPLTIW
Add LXVKQ support.
This patch adds support to generate the LXVKQ instruction to load specific
IEEE-128 floating point constants.
Compared to the last time I submitted this patch, I modified it so that it
uses the bit pattern of the vector to see if it can generate the LXVKQ
instruction. This
Add new constant data structure.
This patch provides the data structure and function to convert a
CONST_INT, CONST_DOUBLE, CONST_VECTOR, or VEC_DUPLICATE of a constant) to
an array of bytes, half-words, words, and double words that can be loaded
into a 128-bit vector register.
The next patches
These patches are a refinement of the patches to add XXSPLTIDP support on
September 13th. These patches generate instructions that load up a VSX
register with certain constants instead of using PLXV to load the constant.
On the Power10:
* XXSPLTIDP is a prefixed instruction that takes a value
On Thu, Sep 09, 2021 at 08:16:16AM +0200, Richard Biener wrote:
> But subreg _is_ bit_cast. What is odd to me is that a "disallowed" subreg
> like (subreg:SF (reg:TI ..) 0) magically becomes valid (in terms of
> validate_subreg) if you rewrite it as (subreg:SF (subreg:SI (reg:TI ..) 0) 0).
> Of
On Tue, Sep 07, 2021 at 06:07:30PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Sep 07, 2021 at 03:12:36AM -0400, Michael Meissner wrote:
> > [PATCH] Fix SFmode subreg of DImode and TImode
> >
> > This patch fixes the breakage in the PowerPC due to a recent change in
> > SUBREG
> >
[PATCH] Fix SFmode subreg of DImode and TImode
This patch fixes the breakage in the PowerPC due to a recent change in SUBREG
behavior. While it is arguable that the patch that caused the breakage should
be reverted, this patch should be a bandage to prevent these changes from
happening again.
I
On Tue, Aug 31, 2021 at 06:41:30PM -0500, Segher Boessenkool wrote:
> Hi!
>
> Please do two separate patches. The first that adds the instruction
> (with a bit pattern, i.e. integer, input), and perhaps a second pattern
> that has an fp as input and uses it if the constant is valid for the
>
On Tue, Aug 31, 2021 at 05:52:48PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Aug 26, 2021 at 05:28:42PM -0400, Michael Meissner wrote:
> > On Thu, Aug 26, 2021 at 02:17:57PM -0500, will schmidt wrote:
> > > On Wed, 2021-08-25 at 15:46 -0400, Michael Meissner wrote:
> > > > Generate
Ping patch.
| Date: Wed, 25 Aug 2021 15:46:43 -0400
| Subject: [PATCH] Generate XXSPLTIDP on power10.
| Message-ID:
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
On Fri, Aug 27, 2021 at 12:29:42PM -0500, Segher Boessenkool wrote:
> On Wed, Aug 25, 2021 at 06:09:44PM -0400, Michael Meissner wrote:
> > I built a compiler on a little endian power8 system where the default long
> > double was IEEE 128-bit instead of IBM 128-bit. I discovered that on
> >
On Fri, Aug 27, 2021 at 11:41:06AM -0500, Bill Schmidt wrote:
> This amuses me, and I want to keep it this way. :-)
> > void store (TYPE a, TYPE *p) { *p = a; }
> > -/* { dg-final { scan-assembler {\mlxvd2x 34\M} {target be} } } */
> > -/* { dg-final { scan-assembler {\mstxvd2x 34\M} {target be}
On Thu, Aug 26, 2021 at 05:28:42PM -0400, Michael Meissner wrote:
> I have patches for adding XXSPLTI32DX, but so far, I'm not sure whether it is
> a
> win or not. This has the xxsplti32dx_operand predicate and the
> xxsplti32dx_constant_p internal function and a separate constraint ("eD") for
>
On Fri, Aug 13, 2021 at 05:22:47PM +, Joseph Myers wrote:
> On Fri, 13 Aug 2021, Andreas Schwab wrote:
>
> > On Aug 12 2021, Patrick McGehearty via Gcc-patches wrote:
> > How can it happen that __LONG_DOUBLE_IEEE128__ is not defined? This
> > file is always compiled with -mfloat128 and this
On Thu, Aug 26, 2021 at 02:17:57PM -0500, will schmidt wrote:
> On Wed, 2021-08-25 at 15:46 -0400, Michael Meissner wrote:
> > Generate XXSPLTIDP on power10.
> >
> > I have added a temporary switch (-mxxspltidp) to control whether or not the
> > XXSPLTIDP instruction is generated.
>
> How
On Wed, Aug 25, 2021 at 05:29:22PM -0500, Segher Boessenkool wrote:
> On Wed, Aug 25, 2021 at 02:22:06PM -0400, Michael Meissner wrote:
> > On Wed, Aug 25, 2021 at 12:44:16PM -0500, Segher Boessenkool wrote:
> > > Out of interest, did you notice any scheduling differences with this?
> >
> > I
>From 327273dfeec5c000f3c33ca7b88ee0097fd33586 Mon Sep 17 00:00:00 2001
From: Michael Meissner
Date: Wed, 25 Aug 2021 00:31:35 -0400
Subject: [PATCH] Fix float128-call.c test for power8 IEEE 128 and power10.
I built a compiler on a little endian power8 system where the default long
double was
Generate XXSPLTIDP on power10.
This patch implements XXSPLTIDP support for SF and DF scalar constants and V2DF
vector constants. The XXSPLTIDP instruction is given a 32-bit immediate that
is converted to a vector of two DFmode constants. The immediate is in SFmode
format, so only constants that
On Wed, Aug 25, 2021 at 12:44:16PM -0500, Segher Boessenkool wrote:
> Hi Mike,
>
> On Wed, Aug 25, 2021 at 12:37:14PM -0400, Michael Meissner wrote:
> > I noticed that the built-functions for xxspltiw, xxspltidp, xxsplti32dx,
> > xxpermx, and xxeval all used the 'vecsimple' type. These
Make xxsplti*, xpermx, xxeval be vecperm type.
I noticed that the built-functions for xxspltiw, xxspltidp, xxsplti32dx,
xxpermx, and xxeval all used the 'vecsimple' type. These instructions are
permute instructions (3 cycle latency) and should use 'vecperm' instead.
While I was at it, I changed
On Wed, Aug 18, 2021 at 06:11:03PM -0500, Segher Boessenkool wrote:
> On Wed, Aug 18, 2021 at 04:42:42PM -0400, David Edelsohn wrote:
> > I wanted to give Segher a chance to comment on the structure.
>
> I think the current vector.md / altivec.md / vsx.md / rs6000.md
> division is artificial at
On Fri, Aug 13, 2021 at 04:33:26PM -0400, David Edelsohn wrote:
> There is a song from Sesame Street: "Which of these is not like the
> others?" altivec.md seems like an outlier. crypto.md and vsx.md also
> seem unusual.
>
> We have
>
> register_operand
> gpc_reg_operand
>
Move xx* builtins to vsx.md.
I originally posted this patch in May. It needed a slight tune up as the
souces have changed, so I'm reposting it now.
I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx,
xxeval, xxblend, and xxpermx) were all defined in altivec.md. However,
Fix xxeval predicates (PR 99921).
I originally posted this patch in May and in June. I'm reposting it now.
I noticed that the xxeval built-in function used the altivec_register_operand
predicate. Since it takes vsx registers, this might force the register
allocate to issue a move when it could
Fix tests that require IBM 128-bit long double
I posted an earlier version of this patch on July 7th, and Segher had some
comments about it on July 14th. This is a revised version of the patch
* My patch: Message-ID: <20210707195837.ga28...@ibm-toto.the-meissners.org>
* Seger's reply:
On Sun, Aug 08, 2021 at 03:21:02PM -0500, Segher Boessenkool wrote:
> On Thu, Aug 05, 2021 at 10:44:36PM -0400, Michael Meissner wrote:
> > * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c: Fix
> > typo in regular expression.
> > *
On Wed, Aug 11, 2021 at 05:55:39AM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Aug 10, 2021 at 04:46:11PM -0600, Sandra Loosemore wrote:
> > OK. I used your wording verbatim for the first one. For the second
> > one, I'm still pretty confused as I think it is at least theoretically
> >
[PATCH] Fix typo in fold-vec-load-builtin_vec_xl-* tests.
When I checked in the fix for running tests on power10 systems with
power10 code generation, I had a typo in the
fold-vec-load-builtin_vec_xl-* tests, swapping 'x' and 'v' in the p?lxv
pattern.
I checked this patch on a little endian
On Thu, Aug 05, 2021 at 12:19:37PM -0600, Sandra Loosemore wrote:
> On 8/5/21 11:33 AM, Michael Meissner wrote:
> >At the moment, we only fully support C and C++ when changing the long double
> >format (between IEEE 128-bit, IBM 128-bit, and 64-bit) when the compiler is
> >invoked (and assuming
On Wed, Aug 04, 2021 at 02:14:07PM -0600, Sandra Loosemore wrote:
> I was trying last week to run my not-yet-committed TS29113 testsuite
> on a powerpc64le-linux-gnu target and ran into some problems with
> the kind constants c_float128 and c_float128_complex from the
> ISO_C_BINDING module; per
On Wed, Jul 14, 2021 at 04:22:06PM -0500, Segher Boessenkool wrote:
> > --- a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
> > +++ b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
>
> > -/* { dg-final { scan-assembler-times "addic" 4 } } */
> > -/* { dg-final { scan-assembler-times "subfe" 1 } } */
On Wed, Jul 14, 2021 at 04:51:52PM -0500, Bill Schmidt wrote:
> Hi Mike,
>
> On 7/14/21 4:42 PM, Michael Meissner wrote:
> >Fix regular expression error in PR 100166 patch
> >
> >In my patch for PR testsuite/100166 (which fixes various tests so that the
> >plxv and pstxv instructions can be
Fix regular expression error in PR 100166 patch
In my patch for PR testsuite/100166 (which fixes various tests so that the
plxv and pstxv instructions can be counted as legitimate instructions), I
had a typo in the pr86731-fwrapv-longlong.c test (using plvx instead of
plxv). This patch fixes
I forgot to add the patch when I reposted this.
PR 100170: Fix eq/ne tests on power10.
This patch updates eq/ne tests in the testsuite to adjust the test if
power10 code generation is used.
2021-07-04 Michael Meissner
gcc/testsuite/
PR testsuite/100170
*
On Wed, Jul 14, 2021 at 11:11:29AM -0500, Bill Schmidt wrote:
> Just for my edification, can you remind me why we need -Wno-psabi?
> What warning are we disabling? Same question for ieee variant.
>
> LGTM in any event. Recommend approval by maintainers...
Unless you configured GCC with a 2.32
On Mon, Jul 12, 2021 at 10:32:47AM -0500, Bill Schmidt wrote:
> Hi Mike,
> >diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
> >b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
> >index 1269fe635c6..d5ed700b9bc 100644
> >---
On Sun, Jul 11, 2021 at 02:55:04PM -0500, Bill Schmidt wrote:
> Hi Mike,
>
> On 7/7/21 3:04 PM, Michael Meissner wrote:
> >[PATCH] PR 100167: Fix vector long long multiply/divide tests on power10.
> >
> >This patch updates the vector long long multiply and divide tests to
> >supply the correct
On Mon, Jul 12, 2021 at 10:49:26AM -0500, Bill Schmidt wrote:
> Hi Mike,
>
> On 7/7/21 3:00 PM, Michael Meissner wrote:
> >[PATCH] Fix vec-splati-runnable.c test.
> >
> >I noticed that the vec-splati-runnable.c did not have an abort after one
> >of the tests. If the test was run with
[PATCH] PR 100168: Fix call test on power10.
Fix a test that was checking for 64-bit TOC calls, to also allow for
PC-relative calls.
I have verified that this test passes when run on a power10 system configured
with --with-cpu=power10 and it continues to pass on power9 little endian and
power8
[PATCH] PR 100170: Fix eq/ne tests on power10.
This patch updates eq/ne tests in the testsuite to adjust the test if
power10 code generation is used.
I have verified that these tests run on a power10 system using the
--with-cpu=power10 configuration option, and they continue to run on power9
[PATCH] PR 100167: Fix vector long long multiply/divide tests on power10.
This patch updates the vector long long multiply and divide tests to
supply the correct code information if power10 code generation is used.
2021-07-07 Michael Meissner
gcc/testsuite/
PR testsuite/100167
201 - 300 of 632 matches
Mail list logo
