Re: [PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

2022-10-21 Thread Richard Earnshaw via Gcc-patches
On 21/09/2022 09:07, Andrea Corallo via Gcc-patches wrote: Hi all, ping^2 for patches 9/15 7/15 11/15 12/15 and 10/15 V2 of this series. Andrea Subject says xx/15, but I only see 1-12 from you. R.

Re: [PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main.

2022-10-21 Thread Richard Earnshaw via Gcc-patches
On 12/08/2022 18:10, Srinath Parvathaneni via Gcc-patches wrote: Hi, This patch supports following -march/-mbranch-protection combination by linking them to existing pacbti multilibs. $ -march=armv8.1-m.main+pacbti+fp.dp+mve.fp -mbranch-protection=standard -mfloat-abi=hard -mthumb $ -mar

Re: [PATCH 10/15 V2] arm: Implement cortex-M return signing address codegen

2022-10-21 Thread Richard Earnshaw via Gcc-patches
On 14/09/2022 15:20, Andrea Corallo via Gcc-patches wrote: Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

2022-10-21 Thread Richard Earnshaw via Gcc-patches
On 27/09/2022 16:24, Kyrylo Tkachov via Gcc-patches wrote: -Original Message- From: Andrea Corallo Sent: Tuesday, September 27, 2022 11:06 AM To: Kyrylo Tkachov Cc: Andrea Corallo via Gcc-patches ; Richard Earnshaw ; nd Subject: Re: [PATCH 9/15] arm: Set again stack pointer as

Re: [PATCH 7/15] arm: Emit build attributes for PACBTI target feature

2022-10-21 Thread Richard Earnshaw via Gcc-patches
On 12/08/2022 16:30, Andrea Corallo via Gcc-patches wrote: This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emi

Re: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM

2022-10-21 Thread Richard Earnshaw via Gcc-patches
On 20/10/2022 18:37, Andrew Pinski via Gcc-patches wrote: On Thu, Oct 20, 2022 at 10:28 AM Segher Boessenkool wrote: On Thu, Oct 20, 2022 at 01:44:15AM +, Jiang, Haochen wrote: Maybe the testcase change cause some misunderstanding and concern. Actually, the patch did not disrupt the p

Re: [PATCH 7/15] arm: Emit build attributes for PACBTI target feature

2022-10-20 Thread Richard Earnshaw via Gcc-patches
On 20/10/2022 15:47, Kyrylo Tkachov via Gcc-patches wrote: Hi Andrea, -Original Message- From: Gcc-patches On Behalf Of Andrea Corallo via Gcc-patches Sent: Friday, August 12, 2022 4:31 PM To: Andrea Corallo via Gcc-patches Cc: Richard Earnshaw ; nd Subject: [PATCH 7/15] arm

Re: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM

2022-10-17 Thread Richard Earnshaw via Gcc-patches
On 14/10/2022 09:34, Haochen Jiang via Gcc-patches wrote: gcc/ChangeLog: * builtins.cc (expand_builtin_prefetch): Handle the fourth parameter in expand function. * config/aarch64/aarch64-sve.md: Add default parameter value. * config/aarch64/aarch64.md (prefetch

Re: [PATCH] [testsuite][arm] Fix cmse-15.c expected output

2022-10-03 Thread Richard Earnshaw via Gcc-patches
On 23/09/2022 09:43, Torbjörn SVENSSON via Gcc-patches wrote: The cmse-15.c testcase fails at -Os because ICF means that we generate secure3: b secure1 which is OK, but does not match the currently expected secure3: ... bx r[0-3] gcc/testsuite/ChangeLog:

Re: [PATCH] arm: Add missing early clobber to MVE vrev64q_m patterns

2022-10-03 Thread Richard Earnshaw via Gcc-patches
On 03/10/2022 11:43, Christophe Lyon via Gcc-patches wrote: Like the non-predicated vrev64q patterns, mve_vrev64q_m_ and mve_vrev64q_m_f need an early clobber constraint, otherwise we can generate an unpredictable instruction: Warning: 64-bit element size and same destination and source opera

Re: [PATCH v2] testsuite: [arm] Relax expected register names in MVE tests

2022-09-30 Thread Richard Earnshaw via Gcc-patches
On 30/09/2022 12:19, Christophe Lyon via Gcc-patches wrote: These two tests have hardcoded q0 as destination/source of load/store instructions, but this register is actually used only under -mfloat-abi=hard. When using -mfloat-abi=softfp, other registers (eg. q3) can be used to transfer functi

Re: [PATCH][committed] aarch64: Suggest an -mcpu option when user passes CPU name to -march

2022-09-05 Thread Richard Earnshaw via Gcc-patches
On 05/09/2022 14:35, Kyrylo Tkachov via Gcc-patches wrote: Hi all, This small patch helps users who confuse -march and -mcpu on AArch64. Sometimes users pass -march with a CPU name, where they most likely wanted to use -mcpu, which would select the right architecture features *and* tune for t

Re: [GCC 13/15][PATCH v3] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

2022-08-19 Thread Richard Earnshaw via Gcc-patches
On 19/08/2022 11:04, Srinath Parvathaneni via Gcc-patches wrote: Hello, This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo hard-register and also .save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for the PAC feature in Armv8.1-M architecture. RA_AUTH_CO

Re: [GCC][PATCH v2] arm: Add support for Arm Cortex-M85 CPU.

2022-08-18 Thread Richard Earnshaw via Gcc-patches
On 12/08/2022 18:20, Srinath Parvathaneni via Gcc-patches wrote: Hi, This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mpcu=cortex-m85 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp.

Re: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

2022-08-18 Thread Richard Earnshaw via Gcc-patches
On 18/08/2022 01:00, Andrew Pinski via Gcc-patches wrote: On Fri, Nov 2, 2018 at 11:39 AM Sudakshina Das wrote: Hi This patch is part of a series that enables ARMv8.5-A in GCC and adds Branch Target Identification Mechanism. (https://developer.arm.com/products/architecture/cpu-architecture

Re: [PATCH] arm: Define with_float to hard when target name ends with hf

2022-08-17 Thread Richard Earnshaw via Gcc-patches
On 17/08/2022 09:35, Christophe Lyon via Gcc-patches wrote: On arm, the --with-float= configure option is used to define include files search path (among other things). However, when targeting arm-linux-gnueabihf, one would expect to automatically default to the hard-float ABI, but this is no

Re: [GCC][PATCH] arm: Add support for Arm Cortex-M85 CPU.

2022-08-05 Thread Richard Earnshaw via Gcc-patches
On 05/08/2022 16:20, Srinath Parvathaneni via Gcc-patches wrote: Hi, This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mpcu=cortex-m85 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp.

Re: [RFA configure parts] aarch64: Make cc1 &co handle --with options

2022-08-05 Thread Richard Earnshaw via Gcc-patches
On 05/08/2022 14:53, Richard Sandiford via Gcc-patches wrote: Richard Earnshaw writes: On 13/06/2022 15:33, Richard Sandiford via Gcc-patches wrote: On aarch64, --with-arch, --with-cpu and --with-tune only have an effect on the driver, so “./xgcc -B./ -O3” can give significantly different

Re: [PATCH v2] cselib: add function to check if SET is redundant [PR106187]

2022-08-03 Thread Richard Earnshaw via Gcc-patches
On 03/08/2022 00:36, Jeff Law wrote: On 8/2/2022 10:06 AM, Richard Earnshaw wrote: On 01/08/2022 11:38, Richard Earnshaw via Gcc-patches wrote: On 30/07/2022 20:57, Jeff Law via Gcc-patches wrote: On 7/29/2022 7:52 AM, Richard Earnshaw via Gcc-patches wrote: A SET operation that

Re: [PATCH v2] cselib: add function to check if SET is redundant [PR106187]

2022-08-02 Thread Richard Earnshaw via Gcc-patches
On 01/08/2022 11:38, Richard Earnshaw via Gcc-patches wrote: On 30/07/2022 20:57, Jeff Law via Gcc-patches wrote: On 7/29/2022 7:52 AM, Richard Earnshaw via Gcc-patches wrote: A SET operation that writes memory may have the same value as an earlier store but if the alias sets of the new

Re: [RFA configure parts] aarch64: Make cc1 &co handle --with options

2022-08-02 Thread Richard Earnshaw via Gcc-patches
On 13/06/2022 15:33, Richard Sandiford via Gcc-patches wrote: On aarch64, --with-arch, --with-cpu and --with-tune only have an effect on the driver, so “./xgcc -B./ -O3” can give significantly different results from “./cc1 -O3”. --with-arch did have a limited effect on ./cc1 in previous relea

Re: [PATCH v2] cselib: add function to check if SET is redundant [PR106187]

2022-08-01 Thread Richard Earnshaw via Gcc-patches
On 30/07/2022 20:57, Jeff Law via Gcc-patches wrote: On 7/29/2022 7:52 AM, Richard Earnshaw via Gcc-patches wrote: A SET operation that writes memory may have the same value as an earlier store but if the alias sets of the new and earlier store do not conflict then the set is not truly

[PATCH v2] cselib: add function to check if SET is redundant [PR106187]

2022-07-29 Thread Richard Earnshaw via Gcc-patches
A SET operation that writes memory may have the same value as an earlier store but if the alias sets of the new and earlier store do not conflict then the set is not truly redundant. This can happen, for example, if objects of different types share a stack slot. To fix this we define a new fu

Re: cselib: add function to check if SET is redundant [PR106187]

2022-07-29 Thread Richard Earnshaw via Gcc-patches
On 29/07/2022 08:06, Richard Biener via Gcc-patches wrote: On Thu, Jul 28, 2022 at 6:46 PM Richard Earnshaw wrote: [resend with correct subject line] A SET operation that writes memory may have the same value as an earlier store but if the alias sets of the new and earlier store do not

cselib: add function to check if SET is redundant [PR106187]

2022-07-28 Thread Richard Earnshaw via Gcc-patches
[resend with correct subject line] A SET operation that writes memory may have the same value as an earlier store but if the alias sets of the new and earlier store do not conflict then the set is not truly redundant. This can happen, for example, if objects of different types share a stack s

http://pdtlreviewboard.cambridge.arm.com/r/16099/

2022-07-28 Thread Richard Earnshaw via Gcc-patches
A SET operation that writes memory may have the same value as an earlier store but if the alias sets of the new and earlier store do not conflict then the set is not truly redundant. This can happen, for example, if objects of different types share a stack slot. To fix this we define a new fu

Re: [PATCH Rust front-end v1 3/4] Add Rust target hooks to ARM

2022-07-27 Thread Richard Earnshaw via Gcc-patches
On 27/07/2022 14:40, herron.philip--- via Gcc-patches wrote: From: Philip Herron This adds the nessecary target hooks for the arm target. gcc/ChangeLog: * config.gcc: add rust_target_objs for arm gcc/config/arm/ChangeLog: * arm-protos.h: define arm_rust_target_cpu_info

Re: [PATCH 9/12 V2] arm: Make libgcc bti compatible

2022-07-25 Thread Richard Earnshaw via Gcc-patches
On 22/07/2022 16:09, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: On 21/07/2022 10:17, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote: This change add bti instructions at the beginning of arm

Re: [PATCH 9/12 V2] arm: Make libgcc bti compatible

2022-07-21 Thread Richard Earnshaw via Gcc-patches
On 21/07/2022 10:17, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote: This change add bti instructions at the beginning of arm specific libgcc hand written assembly routines. 2022-03-31 Andrea Corallo

Re: [PATCH 8/12 V3] arm: Introduce multilibs for PACBTI target feature

2022-07-21 Thread Richard Earnshaw via Gcc-patches
On 21/07/2022 10:04, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: [...] The documentation mentions -mbranch-protection=standard+leaf, so you're missing a mapping for that. OK with that change. R. Oh, and please add some tests to gcc/testsuite/gcc.targe

Re: [PATCH 7/12 V2] arm: Emit build attributes for PACBTI target feature

2022-07-21 Thread Richard Earnshaw via Gcc-patches
On 13/07/2022 09:58, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: On 28/04/2022 10:45, Andrea Corallo via Gcc-patches wrote: This patch emits assembler directives for PACBTI build attributes as defined by the ABI. <https://github.com/ARM-software/abi-aa/releases/downl

Re: [PATCH 5/12 V2] arm: Implement target feature macros for PACBTI

2022-07-21 Thread Richard Earnshaw via Gcc-patches
On 12/07/2022 16:45, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: On 28/04/2022 10:42, Andrea Corallo via Gcc-patches wrote: This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros

Re: [PATCH 4/12] arm: Add testsuite library support for PACBTI target

2022-07-05 Thread Richard Earnshaw via Gcc-patches
On 04/07/2022 15:47, Andrea Corallo wrote: Richard Earnshaw writes: On 01/07/2022 14:03, Richard Earnshaw via Gcc-patches wrote: On 28/04/2022 10:40, Andrea Corallo via Gcc-patches wrote: Add targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested

Re: [PATCH 3/12 V2] arm: Add option -mbranch-protection

2022-07-04 Thread Richard Earnshaw via Gcc-patches
On 04/07/2022 10:27, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw writes: [...] +@item +-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]] +@opindex mbranch-protection +Enable branch protection features

Re: [PATCH 12/12 V2] arm: implement bti injection

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/06/2022 10:21, Andrea Corallo via Gcc-patches wrote: Hi all, second iteration of this patch enabling Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary

Re: [PATCH 11/12] aarch64: Make bti pass generic so it can be used by the arm backend

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:51, Andrea Corallo via Gcc-patches wrote: Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. Best Regards Andrea gcc/Changelog * config.gcc (aarch

Re: [PATCH 10/12 V2] arm: Implement cortex-M return signing address codegen

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/06/2022 10:17, Andrea Corallo via Gcc-patches wrote: Hi all, second version of this patch enabling address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is s

Re: [PATCH 9/12] arm: Make libgcc bti compatible

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote: This change add bti instructions at the beginning of arm specific libgcc hand written assembly routines. 2022-03-31 Andrea Corallo * libgcc/config/arm/crti.S (FUNC_START): Add bti instruction if necessary.

Re: [PATCH 8/12 V2] arm: Introduce multilibs for PACBTI target feature

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 01/07/2022 15:54, Richard Earnshaw via Gcc-patches wrote: On 01/06/2022 13:32, Andrea Corallo via Gcc-patches wrote: Hi all, second iteration of the previous patch adding the following new multilibs: thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch

Re: [PATCH 8/12 V2] arm: Introduce multilibs for PACBTI target feature

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 01/06/2022 13:32, Andrea Corallo via Gcc-patches wrote: Hi all, second iteration of the previous patch adding the following new multilibs: thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/ha

Re: [PATCH 7/12] arm: Emit build attributes for PACBTI target feature

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:45, Andrea Corallo via Gcc-patches wrote: This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emi

Re: [PATCH 6/12] arm: Add pointer authentication for stack-unwinding runtime

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:44, Andrea Corallo via Gcc-patches wrote: This patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEAT

Re: [PATCH 5/12] arm: Implement target feature macros for PACBTI

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:42, Andrea Corallo via Gcc-patches wrote: This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE

Re: [PATCH 4/12] arm: Add testsuite library support for PACBTI target

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 01/07/2022 14:03, Richard Earnshaw via Gcc-patches wrote: On 28/04/2022 10:40, Andrea Corallo via Gcc-patches wrote: Add targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested changes here <https://gcc.gnu.org/pipermail/gcc-patches/2021-Decem

Re: [PATCH 4/12] arm: Add testsuite library support for PACBTI target

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:40, Andrea Corallo via Gcc-patches wrote: Add targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested changes here . gcc/testsuite/ChangeLog: * testsuite/lib/

Re: [PATCH 3/12] arm: Add option -mbranch-protection

2022-07-01 Thread Richard Earnshaw via Gcc-patches
Co-Authored-By: Richard Earnshaw +@item +-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]] +@opindex mbranch-protection +Enable branch protection features (armv8.1-m.main only). +@samp{none} generate code without branch

Re: [PATCH 2/12] arm: Add Armv8.1-M Mainline target feature +pacbti

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:37, Andrea Corallo via Gcc-patches wrote: This patch adds the -march feature +pacbti to Armv8.1-M Mainline. This feature enables pointer signing and authentication instructions on M-class architectures. Pre-approved here

Re: [PATCH 1/12] arm: Make mbranch-protection opts parsing common to AArch32/64

2022-07-01 Thread Richard Earnshaw via Gcc-patches
On 28/04/2022 10:08, Andrea Corallo via Gcc-patches wrote: Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_pars

[committed] arm: more testsutie fallout for mve move-immediate changes

2022-06-20 Thread Richard Earnshaw via Gcc-patches
Unfortunately, there is more fall-out in the testsuite for my changes to use MVE move-immediate operations instead of literal pool loads. Fixed as follows: gcc/testsuite/ChangeLog: * gcc.target/arm/simd/mve-vcmp-f32-2.c: Adjust expected output. * gcc.target/arm/simd/pr100757.c: Li

[committed] arm: fix checking ICE in arm_print_operand [PR106004]

2022-06-17 Thread Richard Earnshaw via Gcc-patches
Sigh, another instance where I incorrectly used XUINT instead of UINTVAL. I've also made the code here a little more robust (although I think this case can't in fact be reached) if the 32-bit clear mask includes bit 31. This case, if reached, would print out an out-of-range value based on the si

[committed] arm: mve: Don't force trivial vector literals to the pool

2022-06-17 Thread Richard Earnshaw via Gcc-patches
A bug in the ordering of the operands in the mve_mov pattern meant that all literal values were being pushed to the literal pool. This patch fixes that and simplifies some of the logic slightly so that we can use as simple switch statement. For example: void f (uint32_t *a) { int i; for (i =

[committed] arm: big-endian issue in gen_cpymem_ldrd_strd [PR105981]

2022-06-15 Thread Richard Earnshaw via Gcc-patches
The code in gen_cpymem_ldrd_strd has been incorrect for big-endian since r230663. The problem is that we use gen_lowpart, etc. to split the 64-bit quantity, but fail to account for the fact that these routines are really dealing with 64-bit /values/ and in big-endian the ordering of the sub-regis

[committed] arm: fix thinko in arm_bfi_1_p() [PR105974]

2022-06-15 Thread Richard Earnshaw via Gcc-patches
I clearly wasn't thinking straight when I wrote the arm_bfi_1_p function and used XUINT rather than UINTVAL when extracting CONST_INT values. It seemed to work in testing, but was incorrect and failed RTL checking. Fixed thusly: gcc/ChangeLog: PR target/105974 * config/arm/arm.

[committed] arm: Improve code generation for BFI and BFC [PR105090]

2022-06-07 Thread Richard Earnshaw via Gcc-patches
This patch, in response to PR105090, makes some general improvements to the code generation when BFI and BFC instructions are available. Firstly we handle more cases where the RTL does not generate an INSV operation due to a lack of a tie between the input and output, but we nevertheless need to e

[committed 2/2] arm: correctly handle misaligned MEMs on MVE [PR105463]

2022-05-13 Thread Richard Earnshaw via Gcc-patches
Vector operations in MVE must be aligned to the element size, so if we are asked for a misaligned move in a wider mode we must recast it to a form suitable for the known alignment (larger elements have better address offset ranges, so there is some advantage to using wider element sizes if possibl

[committed 1/2] arm: fix some issues in mve_vector_mem_operand

2022-05-13 Thread Richard Earnshaw via Gcc-patches
There are a couple of issues with the mve_vector_mem_operand function. Firstly, SP is permitted as a register provided there is no write-back operation. Secondly, there were some cases where 'strict' was not being applied when checking which registers had been used. gcc/ChangeLog: * con

Re: [PATCH] gimple-isel: handle x CMP y ? z : 0

2022-05-04 Thread Richard Earnshaw via Gcc-patches
On 04/05/2022 12:14, Richard Biener wrote: On Wed, May 4, 2022 at 12:16 PM Richard Earnshaw via Gcc-patches wrote: Gimple isel already handles x CMP y ? -1 : 0 when lowering vector cond operations, but this can be generalized further when the comparison forms a natural mask so that we can

[PATCH] gimple-isel: handle x CMP y ? z : 0

2022-05-04 Thread Richard Earnshaw via Gcc-patches
Gimple isel already handles x CMP y ? -1 : 0 when lowering vector cond operations, but this can be generalized further when the comparison forms a natural mask so that we can also handle x CMP y ? z : 0 by transforming it into (x CMP y) & z. This will, in most cases save having to load a register

[pushed] arm: fix testsuite failure of reg_equal_test.c [PR101755]

2022-04-12 Thread Richard Earnshaw via Gcc-patches
The test failure in PR101755 is due to the gimple optimizers getting smarter. But really we are just testing that RTL expansion is doing the right thing and annotating a constant accordingly. So rework the test to use GIMPLE input and simplify the code entirely. Also, this test only ever worked

Re: [PATCH][GCC] arm: remove unnecessary armv9-a multilib variant [PR104144]

2022-04-12 Thread Richard Earnshaw via Gcc-patches
On 08/04/2022 15:48, Przemyslaw Wirkus via Gcc-patches wrote: Hi, This patch is removing unnecessary armv9-a multilib variant which was introduced in commit 32ba7860ccaddd5219e6dae94a3d0653e124c9dd (add armv9-a architecture to -march). Now armv9-a(+simd) multilibs point to already existing ar

Re: [PATCH] aarch64: Restrict aarch64-tune.md regeneration to --enable-maintainer-mode [PR105144]

2022-04-04 Thread Richard Earnshaw via Gcc-patches
On 04/04/2022 13:12, Jakub Jelinek via Gcc-patches wrote: On Mon, Apr 04, 2022 at 12:32:27PM +0100, Richard Earnshaw via Gcc-patches wrote: OK. Thanks, now committed. I think we have a similar issue for arm with arm-tune.md and arm-tables.opt. Perhaps we should adopt a similar approach

Re: [PATCH] aarch64: Restrict aarch64-tune.md regeneration to --enable-maintainer-mode [PR105144]

2022-04-04 Thread Richard Earnshaw via Gcc-patches
On 04/04/2022 11:49, Jakub Jelinek via Gcc-patches wrote: On Mon, Apr 04, 2022 at 11:10:14AM +0100, Richard Sandiford wrote: Normally updates to the source directory files are guarded with --enable-maintainer-mode, e.g. we don't regenerate configure, config.h, Makefile.in in directories that

Re: [PATCH] target/102125 - alternative memcpy folding improvement

2022-03-30 Thread Richard Earnshaw via Gcc-patches
On 23/03/2022 14:57, Richard Biener via Gcc-patches wrote: The following extends the heuristical memcpy folding path with the ability to use misaligned accesses on strict-alignment targets just like the size-based path does. That avoids regressing the following testcase on arm uint64_t

Re: [wwwdocs] Document zero width bit-field passing ABI changes in gcc-12/changes.html [PR104796]

2022-03-30 Thread Richard Earnshaw via Gcc-patches
Never mind, just spotted it. :) On 30/03/2022 13:10, Richard Earnshaw wrote: Doesn't this need the anchor that the compiler links to? #zero_width_bitfields R. On 30/03/2022 11:07, Jakub Jelinek via Gcc-patches wrote: Hi! This patch documents the PR102024 ABI changes. The x86-64, AR

Re: [wwwdocs] Document zero width bit-field passing ABI changes in gcc-12/changes.html [PR104796]

2022-03-30 Thread Richard Earnshaw via Gcc-patches
Doesn't this need the anchor that the compiler links to? #zero_width_bitfields R. On 30/03/2022 11:07, Jakub Jelinek via Gcc-patches wrote: Hi! This patch documents the PR102024 ABI changes. The x86-64, ARM and AArch64 backends refer to this in their -Wpsabi diagnostics. Ok for wwwdocs? diff

Re: [PATCH 1/2] arm: correctly handle zero-sized bit-fields in AAPCS [PR102024]

2022-03-29 Thread Richard Earnshaw via Gcc-patches
On 29/03/2022 17:32, Jakub Jelinek via Gcc-patches wrote: On Tue, Mar 29, 2022 at 04:32:10PM +0100, Richard Earnshaw wrote: On arm the AAPCS states that an HFA is determined by the 'shape' of the object after layout has been completed, so anything that adds no members and does not

[committed] arm: temporarily disable 'local' pcs selection (PR96882)

2022-03-29 Thread Richard Earnshaw via Gcc-patches
The arm port has an optimization used during selection of the function's ABI to permit deviation from the strict ABI when the function does not escape the current translation unit. Unfortunately, the ABI selection it makes can be unsafe if it changes how a result is returned because not enough in

[PATCH 2/2] aarch64: correctly handle zero-sized bit-fields in AAPCS64 [PR102024]

2022-03-29 Thread Richard Earnshaw via Gcc-patches
On aarch64 the AAPCS64 states that an HFA is determined by the 'shape' of the object after layout has been completed, so anything that adds no members and does not cause the layout to be modified should be ignored for the purposes of determining which registers are used for parameter passing. A z

[PATCH 1/2] arm: correctly handle zero-sized bit-fields in AAPCS [PR102024]

2022-03-29 Thread Richard Earnshaw via Gcc-patches
On arm the AAPCS states that an HFA is determined by the 'shape' of the object after layout has been completed, so anything that adds no members and does not cause the layout to be modified should be ignored for the purposes of determining which registers are used for parameter passing. A zero-si

Re: [PATCH] contrib: Avoid use of "echo -n" in git customization [PR102664]

2022-03-10 Thread Richard Earnshaw via Gcc-patches
On 09/03/2022 15:05, Jonathan Wakely via Gcc-patches wrote: On 09/03/22 12:15 +, Richard Earnshaw wrote: The -n option to echo is non-portable.  The generally recommended alternative is to use the shell printf command. contrib/ChangeLog: PR other/102664 * gcc-git

[PATCH] contrib: Avoid use of "echo -n" in git customization [PR102664]

2022-03-09 Thread Richard Earnshaw via Gcc-patches
The -n option to echo is non-portable. The generally recommended alternative is to use the shell printf command. contrib/ChangeLog: PR other/102664 * gcc-git-customization.sh (ask): Use printf instead of echo -n.diff --git a/contrib/gcc-git-customization.sh b/contrib/gcc-git-cus

Re: [PATCH] arm: fix option quoting in error messages.

2022-03-07 Thread Richard Earnshaw via Gcc-patches
On 07/03/2022 10:27, Martin Liška wrote: This fixes option quoting in error messages. Ready to be installed? Thanks, Martin PR target/104794 gcc/ChangeLog: * config/arm/arm.cc (arm_option_override_internal): Fix quoting of options in error messages. (arm_option_reconfig

[committed] aarch64: Adjust spellcheck tests for recent quotation-mark changes

2022-01-21 Thread Richard Earnshaw via Gcc-patches
Martin's recent change to the way we handle quotation marks and punctuation in error messages caused some fallout in the testsuite. This patch updates the tests for the new output. Adjust tests for quotation-mark and punctuation changes. gcc/testsuite: * gcc.target/aarch64/spellche

[PATCH] aarch64: allow ld1/stq in test output [PR102517]

2022-01-20 Thread Richard Earnshaw via Gcc-patches
Following the changes to the inline memcpy operations get expanded, we now generate ld1/st1 using a 128-bit vector register rather than ldp with Q registers. The behaviour is equivalent, so relax the tests to permit either variant. gcc/testsuite/ChangeLog: PR target/102517 * gcc

[PATCH 7/7] arm: Add test for AES erratum mitigation

2022-01-20 Thread Richard Earnshaw via Gcc-patches
Add a testcase for the erratum mitigation. To improve coverage use -dp on the assembler output and match the pattern names (and where needed the alternative number). gcc/testsuite/ChangeLog: * gcc.target/arm/crypto-vaese-erratum1.c: New test. --- .../gcc.target/arm/crypto-vaese-erratum

[PATCH 6/7] arm: elide some cases where the AES erratum workaround is not required.

2022-01-20 Thread Richard Earnshaw via Gcc-patches
Some common cases where the AES erratum workaround are not required are when there are 64- or 128-bit loads from memory, moving a 128-bit value from core registers, and where a 128-bit constant is being loaded from a literal pool. The loads may also be misaligned or generated via a neon intrinsic

[PATCH 5/7] arm: suppress aes erratum when forwarding from aes

2022-01-20 Thread Richard Earnshaw via Gcc-patches
AES operations are commonly chained and since the result of one AES operation is never a 32-bit value, they do not need an additional mitigation instruction for the forwarded result. We handle this common case by adding additional patterns that allow for this. gcc/ChangeLog: * config/ar

[PATCH 4/7] arm: add basic mitigation for Cortex-A AES errata

2022-01-20 Thread Richard Earnshaw via Gcc-patches
This patch adds the basic patterns for mitigation of the erratum, but no attempt is made at this point to optimize the results for the cases where the erratum mitigation is not needed. The mitigation is done by guaranteeing that the input operands are fed from a full-width operation by using an i

[PATCH 3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES

2022-01-20 Thread Richard Earnshaw via Gcc-patches
Add a new option -mfix-cortex-a-aes for enabling the Cortex-A AES erratum work-around and enable it automatically for the affected products (Cortex-A57 and Cortex-A72). gcc/ChangeLog: * config/arm/arm-cpus.in (quirk_aes_1742098): New quirk feature (ALL_QUIRKS): Add it. (c

[PATCH 2/7] arm: Consistently use crypto_mode attribute in crypto patterns

2022-01-20 Thread Richard Earnshaw via Gcc-patches
A couple of patterns in the crypto support code were hard-coding the mode rather than using the iterators. While not incorrect, it was slightly confusing, so adapt those patterns to the style of the rest of the file. Also fix some white space issues. gcc/ChangeLog: * config/arm/crypto.

[PATCH 1/7] arm: Disambiguate multiple crypto patterns with the same name.

2022-01-20 Thread Richard Earnshaw via Gcc-patches
No functional change, but arm/crypto.md has multiple pattenrs all called crypto_, which makes references to them ambiguous, so add the iterator base to the pattern name so that it is distinct in the commit logs. gcc/ChangeLog: * config/arm/crypto.md (crypto_): Add iterator to pat

[committed 0/7] Arm: mitigation for AES erratum on Cortex-a57 and Cortex-A72

2022-01-20 Thread Richard Earnshaw via Gcc-patches
needed. The final patch adds a testcase. Richard Earnshaw (7): arm: Disambiguate multiple crypto patterns with the same name. arm: Consistently use crypto_mode attribute in crypto patterns arm: Add option for mitigating against Cortex-A CPU erratum for AES arm: add basic mitigation for

Re: [ANNOUNCEMENT] Mass rename of C++ .c files to .cc suffix is going to happen on Jan 17 evening UTC TZ

2022-01-18 Thread Richard Earnshaw via Gcc-patches
On 17/01/2022 21:41, Martin Liška wrote: On 1/13/22 12:01, Martin Liška wrote: Hello. Based on the discussion with release managers, the change is going to happen after stage4 begins. Martin Hi. The renaming patches have been just installed and I've built a few target compilers so far

Re: [PATCH] Fix -Wformat-diag for ARM target.

2022-01-13 Thread Richard Earnshaw via Gcc-patches
On 12/01/2022 12:59, Martin Liška wrote: Hello. We've got -Wformat-diag for some time and I think we should start using it in -Werror for GCC bootstrap. The following patch removes last pieces of the warning for ARM target. > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm

Re: [PATCH] Fix -Wformat-diag for aarch64 target.

2022-01-12 Thread Richard Earnshaw via Gcc-patches
On 12/01/2022 09:02, Martin Liška wrote: Hello. We've got -Wformat-diag for some time and I think we should start using it in -Werror for GCC bootstrap. The following patch removes last pieces of the warning for aarch64 target. Ready to be installed? Thanks, Martin OK. R. gcc/ChangeL

Re: [PATCH][GCC] arm: fix __arm_vld1q_z* and __arm_vst1q_p* intrinsics.

2021-12-22 Thread Richard Earnshaw via Gcc-patches
On 22/12/2021 15:55, Murray Steele via Gcc-patches wrote: > Hi All, > > This patch fixes the implementation of the existing __arm_vld1q_z* and > __arm_vst1q_p* MVE intrinsic functions. > > The MVE ACLE allows for __ARM_MVE_PRESERVE_USER_NAMESPACE to be defined, > which removes definitions for int

Re: [PATCH v3 2/2][GCC] arm: Declare MVE types internally via pragma

2021-12-22 Thread Richard Earnshaw via Gcc-patches
On 09/12/2021 15:24, Murray Steele via Gcc-patches wrote: Changes from original patch: 1. Make mentioned changes to changelog. 2. Add namespace-end comments. 3. Add #error for when arm-mve-builtins.def is included without defining DEF_MVE_TYPE. 4. Make placement of '#undef DEF_MVE_TYPE' c

Re: [PATCH 1/2][GCC] arm: Move arm_simd_info array declaration into header

2021-12-22 Thread Richard Earnshaw via Gcc-patches
On 24/11/2021 12:18, Richard Earnshaw via Gcc-patches wrote: On 24/11/2021 12:15, Murray Steele wrote: On 18/11/2021 15:40, Richard Earnshaw wrote: On 16/11/2021 10:14, Murray Steele via Gcc-patches wrote: Hi all, This patch moves the arm_simd_type and arm_type_qualifiers enums, and

Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen

2021-12-17 Thread Richard Earnshaw via Gcc-patches
On 17/12/2021 15:52, Andrea Corallo wrote: Hi Richard, thanks for reviewing! Some comments inline. Richard Earnshaw writes: On 05/11/2021 08:52, Andrea Corallo via Gcc-patches wrote: Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer

Re: [Patch 7/8 V2] Arm: Emit build attributes for PACBTI target feature.

2021-12-10 Thread Richard Earnshaw via Gcc-patches
On 10/12/2021 16:36, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw via Gcc-patches writes: On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: -Original Message- From: Gcc-patches On Behalf Of Tejas Belagod via Gcc-patches Sent: Friday, October 8, 2021 1:19 PM To

Re: [Patch 7/8 V2] Arm: Emit build attributes for PACBTI target feature.

2021-12-10 Thread Richard Earnshaw via Gcc-patches
On 10/12/2021 16:36, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw via Gcc-patches writes: On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: -Original Message- From: Gcc-patches On Behalf Of Tejas Belagod via Gcc-patches Sent: Friday, October 8, 2021 1:19 PM To

Re: [Patch 6/8 V2] Arm: Add pointer authentication for stack-unwinding runtime.

2021-12-10 Thread Richard Earnshaw via Gcc-patches
On 09/12/2021 17:36, Andrea Corallo via Gcc-patches wrote: Richard Earnshaw via Gcc-patches writes: On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: -Original Message- From: Gcc-patches On Behalf Of Tejas Belagod via Gcc-patches Sent: Friday, October 8, 2021 1:18 PM To

Re: [PATCH 2/2][GCC] arm: Declare MVE types internally via pragma

2021-12-08 Thread Richard Earnshaw via Gcc-patches
On 08/12/2021 15:39, Murray Steele via Gcc-patches wrote: > Hi, > > Thank you for the feedback, I'll make the noted changes to the changelog and > add the missing end-of-namespace comments. > > On 08/12/2021 15:23, Richard Earnshaw wrote: > >> diff --git a/gcc

Re: [patch, Fortran] IEEE support for aarch64-apple-darwin

2021-12-08 Thread Richard Earnshaw via Gcc-patches
On 08/12/2021 15:47, FX via Gcc-patches wrote: Hi Richard, This isn't a full review, but I do have a question: is this really specific to Darwin? or is it really generic aarch64 code? If the former, then the file name is not right and it should reflect the darwin-specific nature of the

Re: [patch, Fortran] IEEE support for aarch64-apple-darwin

2021-12-08 Thread Richard Earnshaw via Gcc-patches
On 06/12/2021 16:32, FX via Gcc-patches wrote: Hi everyone, Since support for target aarch64-apple-darwin has been submitted for review, it’s time to submit the Fortran part, i.e. enabling IEEE support on that target. The patch has been in use now for several months, in a developer branch s

Re: [PATCH 2/2][GCC] arm: Declare MVE types internally via pragma

2021-12-08 Thread Richard Earnshaw via Gcc-patches
On 25/11/2021 09:42, Murray Steele via Gcc-patches wrote: Changes from original patch: 1. Merged test_redef_* test files into one 2. Encapsulated contents of arm-mve-builtins.h in namespace arm_mve (missed in initial patch). 3. Added extern declarations for scalar_types and acle_vector ty

Re: [PATCH] [2/2] arm: add arm bti pass

2021-12-08 Thread Richard Earnshaw via Gcc-patches
On 05/11/2021 08:55, Andrea Corallo via Gcc-patches wrote: Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by moving and generalizing the Aarch64 "bti" pass so it can be used also by the Arm backend. The pass iterates through the instruction

Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen

2021-12-08 Thread Richard Earnshaw via Gcc-patches
On 05/11/2021 08:52, Andrea Corallo via Gcc-patches wrote: Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP

Re: [Patch 8/8, Arm, GCC] Introduce multilibs for PACBTI target feature. [Was RE: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI target feature.]

2021-12-07 Thread Richard Earnshaw via Gcc-patches
On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: -Original Message- From: Gcc-patches On Behalf Of Tejas Belagod via Gcc-patches Sent: Friday, October 8, 2021 1:19 PM To: gcc-patches@gcc.gnu.org Subject: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI target feature.

Re: [Patch 7/8, Arm, GCC] Emit build attributes for PACBTI target feature. [ Was RE: [Patch 6/7, Arm, GCC] Emit build attributes for PACBTI target feature.]

2021-12-07 Thread Richard Earnshaw via Gcc-patches
On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: -Original Message- From: Gcc-patches On Behalf Of Tejas Belagod via Gcc-patches Sent: Friday, October 8, 2021 1:19 PM To: gcc-patches@gcc.gnu.org Subject: [Patch 6/7, Arm, GCC] Emit build attributes for PACBTI target feature

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