Thanks for supporting vf/vx transforming.
I'd rather let Robin review this patch.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-07-17 18:55
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: More support of vx and vf for autovec comparison
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-11 16:29
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
From: Pan Li
This patch would like to add the test cases for the vector
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-08 14:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
From: Pan Li
This patch would like to implement the .SAT_TRUNC for the RISC-V
+ if (double_mode == E_VOIDmode && quad_mode == E_VOIDmode)
Why we have VOID mode ? I still don't understand the codes.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-08 12:48
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v2] RISC-V: I
ook odd to me. Could you optimize it in a more straightforward way?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-05 09:23
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
From: Pan Li
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-07-03 17:39
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; Li, Pan2
Subject: [PATCH] RISC-V: Use tu policy for first-element vec_set [PR115725].
Hi,
this patch changes the tail policy for vmv.s.x
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-03 13:22
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
From: Pan Li
It seems that the asm check is incorrect for truncated after
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 1
From: Pan Li
This patch would like to add test cases
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 4
From: Pan Li
This patch would like to add test cases
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 2
From: Pan Li
This patch would like to add test cases
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 3
From: Pan Li
This patch would like to add test cases
Since middle-end patch is approved, LGTM this patch.
Thanks for improving RVV vectorization.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-25 20:40
To: gcc-patches
CC: juzhe.zhong; kito.cheng; richard.guenther; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add testcases
I see, it's operator== overloaded.
LGTM.
juzhe.zh...@rivai.ai
From: wangf...@eswincomputing.com
Date: 2024-06-21 17:03
To: juzhe.zhong; gcc-patches
CC: kito.cheng; jinma.contrib
Subject: Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
On 2024-06-21 12:24 juzhe.zhong wrote
;
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch
LGTM
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 1/3] RISC-V: Add vector type of BFloat16 format
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form
10
From: Pan Li
After the middle-end support the form 10 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
From: Pan Li
After the middle-end support the form 8 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
From: Pan Li
After the middle-end support the form 4 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
From: Pan Li
After the middle-end support the form 7 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
From: Pan Li
After the middle-end support the form 6 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
From: Pan Li
After the middle-end support the form 9 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
From: Pan Li
After the middle-end support the form 5 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li
After the middle-end support the form 3 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-13 16:26
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction
mismatch
From: Pan Li
We have vec_extract pattern which takes ZVFHMIN
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 5/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5
From: Pan Li
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 4/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4
From: Pan Li
After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 2/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2
From: Pan Li
After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 3/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3
From: Pan Li
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1
From: Pan Li
After the middle-end support the form 1 of unsigned SAT_ADD and
the RISC
some one backport them to GCC-14 ?
Thanks.
juzhe.zh...@rivai.ai
CC Robin who knows better than me in case of scheduling model in RISC-V
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-05-20 15:59
To: gcc-patches
CC: kito.cheng; palmer; tamar.christina; richard.guenther; Richard.Sandiford;
juzhe.zhong; zhengyu; pan2.li; xuli
Subject: [PATCH] RISC-V: Enable
LGTM.
juzhe.zh...@rivai.ai
RISC-V part LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-16 12:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; tamar.christina; richard.guenther;
Richard.Sandiford; Pan Li
Subject: [PATCH v2 3/3] RISC-V: Enable vectorizable early exit testsuite
From: Pan Li
After we supported
RISC-V part LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-16 12:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; tamar.christina; richard.guenther;
Richard.Sandiford; Pan Li
Subject: [PATCH v2 2/3] RISC-V: Implement vectorizable early exit with
vcond_mask_len
From: Pan Li
After
LGTM from my side. Wait for kito chime in.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-11 15:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar
From: Pan Li
For the vfw vx format RVV intrinsic
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-09 11:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
From: Pan Li
During investigate the support of early break autovec, we notice
the test full-vec
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-05-07 09:17
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li
CC: Kito Cheng
Subject: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]
vsetvli local eliminate is only consider the current demand
Hi, Han.
GCC 14 is branch out. You can commit it to trunk (GCC 15).
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV
cost
LGTM from my side. But give kito more time chime in.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-28 11:53
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg
const_poly_move
From: Pan Li
When we build with isl
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-04-25 19:23
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; Patrick
O'Neill
Subject: [PATCH] RISC-V: Add testcase for PR114749.
Hi,
this adds a test case for PR114749.
Going to commit as obvious
LGTM. THANKS
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 17:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li; Kito Cheng
Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
From: Pan Li
We have one ICE when RVV register
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap
of vwcvt
From: Pan Li
We reverted below patch for register group overlap, add
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
From: Pan Li
We missed the existing early clobber for the dest operand of vwsll
pattern when
lgtm.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-04-24 18:09
To: gcc-patches; kito.cheng; rdapp; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]
extract_single_source will recursive checking the sources to
make sure if it's single
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-24 10:48
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf
From: Pan Li
We reverted below patch for register group overlap, add the related
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 16:27
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap
floating-point widen insn
From: Pan Li
We reverted below patch for register group overlap, add
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 15:43
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v2] RISC-V: Add xfail test case for indexed load overlap with
SRC EEW < DEST EEW
From: Pan Li
Update in v2:
* Add change log to pr112431-3
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 14:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highest-number regno
ternary overlap
From: Pan Li
We reverted below patch for register group overlap, add
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 11:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for widening register overlap
of vf4/vf8
From: Pan Li
We reverted below patch for register group overlap, add
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-20 09:04
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
From: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-42.c: New
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-12 14:08
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
From: Pan Li
This patch would like to fix one ICE when vector is not enabled
in hook
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-11 11:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Remove -Wno-psabi for test build option [NFC]
From: Pan Li
Just notice there are some test case still have -Wno-psabi option,
which is deprecated
Thanks for fixing it. LGTM from my side.
I prefer wait kito for another ACK.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-11 10:16
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch
From: Pan Li
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-08 16:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Refine the error msg for RVV intrinisc required ext
From: Pan Li
The RVV intrinisc API has sorts of required extension from both
the march
It's obvious fix to previous incorrect typo.
So LGTM to trunk (GCC-14).
Thanks.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: Minor fix for max_point
The program points start
Thanks for fixing it. LGTM to GCC-15 as Jeff suggested.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV
cost model
OK. It's an obvious fix but it seems to be unrelated to the PR.
Could you split it 2 separate patches ?
Thanks.
juzhe.zh...@rivai.ai
发件人： Demin Han
发送时间： 2024-03-28 19:06
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： kito.cheng; pan2.li; jeffreyalaw; Robin Dapp
主题： RE: [PATCH] RISC-V: Refine
Thanks a lot for trying to optimize the dynamic LMUL cost model.
The need_additional_vector_vars_p looks good to me.
But
- = (*program_points_per_bb.get (bb)).length () - 1;
+ = (*program_points_per_bb.get (bb)).length ();
I wonder why you remove - 1?
juzhe.zh
I think it's harmless to let this patch in GCC-14.
So LGTM from my side to land this path in GCC-14..
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-26 01:07
To: Jeff Law; 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add initial cost handling
LGTM.
juzhe.zh...@rivai.ai
From: Christoph Müllner
Date: 2024-03-22 07:45
To: gcc-patches; Kito Cheng; Palmer Dabbelt; Andrew Waterman; Philipp Tomsich;
Camel Coder; Bruce Hoult; Juzhe-Zhong; Jun Sha; Xianmiao Qu; Jin Ma
CC: Christoph Müllner
Subject: [PATCH] RISC-V: Don't add fractional
I can't review this stuff. Let kito review this.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-18 14:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
From: Pan Li
This p
ould it really be called autovec-max-lmul? We also use TARGET_MAX_LMUL
>>for builtins etc. Or are we just following LLVM's naming here?
>>Isn't -mrvv-max-lmul sufficient?
The original option is kito's recommandation. Both -mrvv-max-lmul and
-mrvv-autovec-max-lmul are ok for me.
juz
LGTM except a nit comment:
PR 114264 -> PR target/114264
No need to send V3, just commit it with this change.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 16:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH v2] RISC-V: Fix ICE in riscv vec
I suggest open an PR with a PR id.
juzhe.zh...@rivai.ai
发件人： Demin Han
发送时间： 2024-03-07 15:39
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： kito.cheng; pan2.li; jeffreyalaw
主题： RE: [PATCH] RISC-V: Fix ICE in riscv vector costs
OK.
Which is better for testcase name?
1. ice-biggestmode.c or
2
Could you plz add testcase ? I just noticed you didn't append a testcase (jpeg)
in this patch.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 13:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The following
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 13:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The following code can result in ICE:
-march=rv64gcv_zba_zbb --param riscv-autovec-lmul=dynamic -O3
char
Thanks for support it.
I leave this patch review to kito who is much more familiar with it than me.
CCing more folks who may be interested at this stuff.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-06 14:38
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject
Hi, han.
I think you can commit this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/646931.html
RISC-V: Refactor expand_vec_cmp
It's an NFC patch that I approved.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-04 14:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng
Subject
LGTM. Thanks for clean up.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-05 16:59
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]
From: Pan Li
Cleanup mode_size related code which
: (vec_duplicate) (reg)))
juzhe.zh...@rivai.ai
From: Demin Han
Date: 2024-03-05 16:40
To: 钟居哲; gcc-patches
CC: kito.cheng; Li, Pan2; jeffreyalaw; Robin Dapp; richard.sandiford
Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of
vec and imm
Hi,
I applied
Could you rebase to the trunk ? I don't think segment load store cost depends
on previous patch you sent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-01 23:07
To: 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc; Jeff Law
Subject: Re: [PATCH] RISC-V: Add initial cost handling
should remove them.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-02-28 22:55
To: 钟居哲
CC: pan2.li; gcc-patches; yanzhang.wang; rdapp.gcc; Jeff Law
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for
RVV
Hmm, maybe only keep --param=riscv-autovec-preference=none
I suggest specify -fno-schedule-insns to force tests assembler never change for
any scheduling model.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-02-28 08:55
To: jeffreyalaw
CC: juzhe.zhong; Robin Dapp; ewlu; gcc-patches; gnu-toolchain; pan2.li
Subject: Re: [PATCH] RISC-V: Update
Thanks for supporting this.
I'd rather leave this patch review to kito's since it's kito's proposal.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-02-27 09:17
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; xuli
Subject: [PATCH] RISC-V: Add riscv_vector_cc function attribute
From
If the scheduling model increases the vsetvls, we shouldn't set it as default
scheduling model
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-26 21:29
To: Edwin Lu; gcc-patches
CC: rdapp.gcc; gnu-toolchain; pan2.li; juzhe.zh...@rivai.ai
Subject: Re: [PATCH] RISC-V: Update test
(kind, stmt_info))
{
case 2:
stmt_cost += simd_costs->ld2_st2_permute_cost;
break;
case 3:
stmt_cost += simd_costs->ld3_st3_permute_cost;
break;
case 4:
stmt_cost += simd_costs->ld4_st4_permute_cost;
break;
}
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-26 23:54
To: gc
eturn DR_GROUP_SIZE (stmt_info);
}
return 0;
}
juzhe.zh...@rivai.ai
.
But I'd like to CC more RISC-V GCC folks to see the votes.
If most of the people don't want this in GCC-14 and defer it to GCC-15, I won't
insist on it.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-23 16:29
To: Kito Cheng; pan2.li
CC: gcc-patches; juzhe.zhong; yanzhang.wang
Sorry, I missed review the testcase:
+/* { dg-final { scan-assembler-times "vmv\.v\.i\tv\[0-9\],0" 0 } } */
I think you should use "scan-assembler-not"
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-23 04:02
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@ri
lgtm.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-23 04:02
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai
CC: rdapp.gcc; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].
Hi,
for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try
Ping this patch which is simple fix on VSETVL PASS.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2024-02-01 17:02
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH v2] RISC-V: Suppress the vsetvl fusion for conflict successors
Hi, Robin. Could you continue on this LICM issue ?
I am not sure whether my fix is correct, or you may find another way to make
LICM works ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-06 21:14
To: juzhe.zh...@rivai.ai; kito.cheng
CC: rdapp.gcc; gcc-patches; Kito.cheng; jeffreyalaw
Why is it 2 not 1 or other value ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-02-07 17:27
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function
checker
From: Pan Li
There is another corn case
Did you run the C compiler compile C++ intrinsic test ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-02-06 16:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty
args
From: Pan Li
I think it just trigger a latent bug that we didn't encounter.
Hi, Robin. Would you mind give me preprocessed file to reproduce the issue ?
I suspect it triggers latent bug in VSETVL PASS.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-05 12:36
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng
a/gcc/loop-iv.cc b/gcc/loop-iv.cc
index eb7e923a38b..09750951845 100644
--- a/gcc/loop-iv.cc
+++ b/gcc/loop-iv.cc
@@ -646,10 +646,10 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode,
rtx reg,
if (!set)
return false;
- rhs = find_reg_equal_equiv_note (insn);
- if (rhs)
-rhs
Thanks. I wonder whether p600 will enable dynamic lmul by default ?
Does dynamic LMUL help with sifive p600 chip ?
juzhe.zh...@rivai.ai
From: Monk Chiang
Date: 2024-02-01 16:10
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive
/riscv-avlprop.cc:200
0x1fe3b05 pass_avlprop::execute(function*)
../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:506
Would you mind taking a look at it ?
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c (test for excess errors)
Your patch is good.
Thanks for the help.
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng; jeffreyalaw; palmer; vineetg
Maybe I do the wrong testing. Let me use a clean linux environment and try
again.
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng; jeffreyalaw; palmer; vineetg; Patrick O'Neill
Subject: Re: [COMMITTED V3 1/4] RISC-V
Hi, Monk.
This model doesn't include vector. Will you add vector pipeline in the
followup patches ?
juzhe.zh...@rivai.ai
ad_64-12.c (internal
compiler error: in validate_change_or_fail, at config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c
(internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-v.cc:4972)
juzhe.zh...@rivai.ai
ok
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-27 10:50
To: gcc-patches
CC: juzhe.zhong; Patrick O'Neill
Subject: [PATCH] RISC-V: Add require-effective-target to pr113429 testcase
The pr113429 testcase fails with newlib spike runs. Adding
require-effective-target rv64
It's fixed by this commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d40b3c1e439db05c835b6bd4fd5bba58fda71dd6
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-01-17 09:45
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Patrick O'Neill
Subject: Re: [Committed V2] RISC-V: Fix regression (GCC-14
rv64 } */
/* { dg-require-effective-target riscv_v } */
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-24 09:20
To: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng; law; rdapp; vineetg
Subject: [Committed] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcase
-final { scan-assembler-not {csrr} } } */
This needs a XFAIL, I am not sure whether the spiling is reasonable, so XFAIL
this case.
We will analyze this case whether it is reasonable.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-25 15:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2
ok
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-24 08:50
To: gcc-patches
CC: juzhe.zhong; kito.cheng; law; rdapp; vineetg; Patrick O'Neill
Subject: [PATCH] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcase for pr113429 (cam4 failure) needed additional
No, we didn't undo the optimization.
We just disallow move pattern for (set (reg) (VL_REGNUM)).
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-22 19:25
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix regressions due
OK I guess change register_operand into REG_P should fix those ICEs.
I will have a try and send a patch.
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-22 15:14
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; kito.cheng; jeffreyalaw; vineetg; Robin Dapp;
palmer
-O3 -g (test for excess errors)
FAIL: gcc.dg/torture/pr48124-4.c -Os (internal compiler error: in
reg_or_subregno, at jump.cc:1895)
FAIL: gcc.dg/torture/pr48124-4.c -Os (test for excess errors)
juzhe.zh...@rivai.ai
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