eers,
>>> Andre
>>>
>>>
>>> From: Richard Sandiford
>>> Sent: Thursday, June 14, 2018 12:28:16 PM
>>> To: Andre Simoes Dias Vieira
>>> Cc: gcc-patches@gcc.gnu.org; nd
>>> Subject: Re: [A
_
> > From: Richard Sandiford
> > Sent: Thursday, June 14, 2018 12:28:16 PM
> > To: Andre Simoes Dias Vieira
> > Cc: gcc-patches@gcc.gnu.org; nd
> > Subject: Re: [AArch64][PATCH 1/2] Fix addressing printing of LDP/STP
> >
> > Andre Sim
quot;narrowing". So we should leave that one as
> is.
>
> Cheers,
> Andre
>
>
> From: Richard Sandiford
> Sent: Thursday, June 14, 2018 12:28:16 PM
> To: Andre Simoes Dias Vieira
> Cc: gcc-patches@gcc.gnu.org; nd
> Subjec
_
From: Richard Sandiford
Sent: Thursday, June 14, 2018 12:28:16 PM
To: Andre Simoes Dias Vieira
Cc: gcc-patches@gcc.gnu.org; nd
Subject: Re: [AArch64][PATCH 1/2] Fix addressing printing of LDP/STP
Andre Simoes Dias Vieira writes:
> @@ -5716,10 +5717,17 @@ aarch64_classify_ad
Andre Simoes Dias Vieira writes:
> @@ -5716,10 +5717,17 @@ aarch64_classify_address (struct aarch64_address_info
> *info,
>unsigned int vec_flags = aarch64_classify_vector_mode (mode);
>bool advsimd_struct_p = (vec_flags == (VEC_ADVSIMD | VEC_STRUCT));
>bool load_store_pair_p = (type
Hi Andre,
On 07/06/18 18:01, Andre Simoes Dias Vieira wrote:
Hi,
The address printing for LDP/STP patterns that don't use parallel was not
working properly when dealing with a post-index addressing mode. The post-index
address printing uses the mode's size to determine the post-index
Hi,
The address printing for LDP/STP patterns that don't use parallel was not
working properly when dealing with a post-index addressing mode. The post-index
address printing uses the mode's size to determine the post-index immediate.
To fix an earlier issue with range checking of these
