On Fri, Jun 16, 2017 at 05:55:35PM -0400, Michael Meissner wrote:
> Here is the latest patch that restricts the optimization to 64-bit (due to
> needing VSX small integers). I've done a full bootstrap/make check on a
> little
> endian power8 system, and a build without bootstrap and make check
On Fri, Jun 16, 2017 at 04:30:48PM -0500, Segher Boessenkool wrote:
> On Fri, Jun 16, 2017 at 04:26:58PM -0400, Michael Meissner wrote:
> > > > + "&& reload_completed"
> > >
> > > I still don't think it is such a good idea to do all of this not until
> > > after reload. It does of course allow
On Fri, Jun 16, 2017 at 04:26:58PM -0400, Michael Meissner wrote:
> > > + "&& reload_completed"
> >
> > I still don't think it is such a good idea to do all of this not until
> > after reload. It does of course allow you to play tricks with changing
> > register mode at will, like you do ;-)
>
On Fri, Jun 16, 2017 at 02:52:46PM -0500, Segher Boessenkool wrote:
> Hi Mike,
>
> On Thu, Jun 15, 2017 at 10:10:28PM -0400, Michael Meissner wrote:
> > +(define_insn_and_split "vsx_set_v4sf_p9"
> > + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
> > + (unspec:V4SF
> > +
Hi Mike,
On Thu, Jun 15, 2017 at 10:10:28PM -0400, Michael Meissner wrote:
> +(define_insn_and_split "vsx_set_v4sf_p9"
> + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
> + (unspec:V4SF
> + [(match_operand:V4SF 1 "gpc_reg_operand" "0")
> + (match_operand:SF 2
On Thu, Jun 15, 2017 at 07:39:39PM -0400, Michael Meissner wrote:
> I thought the patch was fine as I posted. I had an optimization I thought
> about (optimizing for inserting 0.0f) and I noticed some problems with it.
> However, even in backing out the change, there are some problems. So, I
