Re: [PATCH] Prefer shorter VEX encoding of VP{AND,OR,XOR,ANDN} over EVEX when possible (PR target/82370)

2017-10-19 Thread Kirill Yukhin
Hello Jakub, Uroš, On 04 Oct 13:41, Uros Bizjak wrote: > On Wed, Oct 4, 2017 at 10:33 AM, Jakub Jelinek wrote: > > Hi! > > > > Most AVX* instructions have the same insn name between VEX and EVEX > > encoded insns and whether it is EVEX or VEX encoded is determined by > > the

Re: [PATCH] Prefer shorter VEX encoding of VP{AND,OR,XOR,ANDN} over EVEX when possible (PR target/82370)

2017-10-04 Thread Uros Bizjak
On Wed, Oct 4, 2017 at 10:33 AM, Jakub Jelinek wrote: > Hi! > > Most AVX* instructions have the same insn name between VEX and EVEX > encoded insns and whether it is EVEX or VEX encoded is determined by > the operands by the assembler (if there is masking/broadcast, or >

[PATCH] Prefer shorter VEX encoding of VP{AND,OR,XOR,ANDN} over EVEX when possible (PR target/82370)

2017-10-04 Thread Jakub Jelinek
Hi! Most AVX* instructions have the same insn name between VEX and EVEX encoded insns and whether it is EVEX or VEX encoded is determined by the operands by the assembler (if there is masking/broadcast, or %[xy]mm16+ operands are present, or when using 512-bit vectors). This is not the case for