[PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-07 Thread Raphael Moreira Zinsly
gcc/ChangeLog: * config/riscv/riscv-cores.def: Add veyron-v1 core and tune info. * config/riscv/riscv-opts.h (riscv_microarchitecture_type): Add veyron-v1. * config/riscv/riscv.cc (veyron_v1_tune_info): New. * config/riscv/riscv.md: Include veyron-v1

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-07 Thread Kito Cheng via Gcc-patches
I would like vendor cpu name start with vendor name, like ventana-veyron-v1 which is consistent with all other vendor cpu, and llvm are using same convention too. Raphael Moreira Zinsly 於 2023年6月7日 週三，21:18寫道： > gcc/ChangeLog: > > * config/riscv/riscv-cores.def: Add veyron-v1 > co

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-07 Thread Jeff Law via Gcc-patches
On 6/7/23 08:13, Kito Cheng wrote: I would like vendor cpu name start with vendor name, like ventana-veyron-v1 which is consistent with all other vendor cpu, and llvm are using same convention too. Fair enough. Better to get it right now than have this stuff be inconsistent. It'll be a lit

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-07 Thread Jeff Law via Gcc-patches
On 6/7/23 08:43, Jeff Law wrote: On 6/7/23 08:13, Kito Cheng wrote: I would like vendor cpu name start with vendor name, like ventana-veyron-v1 which is consistent with all other vendor cpu, and llvm are using same convention too. Fair enough.  Better to get it right now than have this stu

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-08 Thread Kito Cheng via Gcc-patches
> diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > index 7d87ab7ce28..4078439e562 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) > RISCV_TUNE(

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-08 Thread Philipp Tomsich
On Thu 8. Jun 2023 at 09:35, Kito Cheng via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > > diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > > index 7d87ab7ce28..4078439e562 100644 > > --- a/gcc/config/riscv/riscv-cores.def > > +++ b/gcc/config/riscv/riscv-cor

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-08 Thread Kito Cheng via Gcc-patches
> On Thu 8. Jun 2023 at 09:35, Kito Cheng via Gcc-patches < > gcc-patches@gcc.gnu.org> wrote: > > > > diff --git a/gcc/config/riscv/riscv-cores.def > > b/gcc/config/riscv/riscv-cores.def > > > index 7d87ab7ce28..4078439e562 100644 > > > --- a/gcc/config/riscv/riscv-cores.def > > > +++ b/gcc/config/

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-08 Thread Jeff Law via Gcc-patches
On 6/8/23 04:22, Kito Cheng wrote: Oh, okay I got the awkness point...I am ok with that on gcc land, but I would like binutils support that first, or remove the extension from the mcpu for temporary before binutils support, otherwise it just a broken support for that CPU on trunk gcc. I

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-08 Thread Philipp Tomsich
On Thu 8. Jun 2023 at 16:17, Jeff Law wrote: > > > On 6/8/23 04:22, Kito Cheng wrote: > > > > > > > Oh, okay I got the awkness point...I am ok with that on gcc land, but I > > would like binutils support that first, or remove the extension from the > > mcpu for temporary before binutils support,

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

2023-06-08 Thread Kito Cheng via Gcc-patches
> > I'd very much like to see the condops go into GCC as well, but I've been > > hesitant to move it forward myself. We're still waiting on hardware and > > it wasn't clear to me that we really had consensus agreement to move the > > bits forward based on an announcement vs waiting on actual hardw