Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Robin, I have posted a V2 patch to implement the method I mentioned. I wonder if that makes it a little easier to understand? V2 patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630985.html On 2023/9/20 12:02, Lehua Ding wrote: On 2023/9/20 6:02, Robin Dapp wrote: Hi

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

On 2023/9/20 6:02, Robin Dapp wrote: Hi Lehua, thanks for the explanation. My current method is still to keep the operand 2 of vcond_mask as a register, but the pattern of mov_vec_const_0 is simplified, so that the corresponding combine pattern can be more simple. That's the only reason I

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Lehua, thanks for the explanation. > My current method is still to keep the operand 2 of vcond_mask as a > register, but the pattern of mov_vec_const_0 is simplified, so that > the corresponding combine pattern can be more simple. That's the only > reason I split the vcond_mask into three

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Robin, Would it hurt to allow any nonmemory operand here and just force the "unsupported" constants into a register? Are you talking about why operand 2 doesn't use nonmemory_operand predicate? If so, I think this is because our vmerge.v[vxi]m insns only supports that operand 1 is a scalar

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Lehua, >> Would it hurt to allow any nonmemory operand here and just force the >> "unsupported" constants into a register? > > Are you talking about why operand 2 doesn't use nonmemory_operand > predicate? If so, I think this is because our vmerge.v[vxi]m insns > only supports that operand 1

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Robin, +(define_expand "vcond_mask_" + [(set (match_operand:V_VLS 0 "register_operand") +(if_then_else:V_VLS + (match_operand: 3 "register_operand") + (match_operand:V_VLS 1 "nonmemory_operand") + (match_operand:V_VLS 2

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Lehua, > +(define_expand "vcond_mask_" > + [(set (match_operand:V_VLS 0 "register_operand") > +(if_then_else:V_VLS > + (match_operand: 3 "register_operand") > + (match_operand:V_VLS 1 "nonmemory_operand") > + (match_operand:V_VLS 2

[PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

This patch support combining cond extend and reduce_sum to cond widen reduce_sum like combine the following three insns: (set (reg:RVVM2HI 149) (const_vector:RVVM2HI repeat [ (const_int 0) ])) (set (reg:RVVM2HI 138) (if_then_else:RVVM2HI (reg:RVVMF8BI 135)