This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
PR target/111391
gcc/ChangeLog:
* config/riscv/autovec.md (@vec_extract): Remove @.
(vec_extract): Ditto.
* config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
(pass_vsetvl::local_e
I am thinking what we are doing is something like we are allowing
scalar mode within the vector register, so...not sure should we try to
implement that within the mov pattern?
I guess we need some inputs from Jeff.
e.g.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0ec
> I am thinking what we are doing is something like we are allowing
> scalar mode within the vector register, so...not sure should we try to
> implement that within the mov pattern?
>
> I guess we need some inputs from Jeff.
Sorry for the late response. I have also been thinking about this and
i
*To:* Juzhe-Zhong <mailto:juzhe.zh...@rivai.ai>
*CC:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>; kito.cheng
<mailto:kito.ch...@sifive.com>; jeffreyalaw
<mailto:jeffreya...@gmail.com>; rdapp.gcc <mailto:rdapp....@gmail.com>
*Subject:* Re: [PATCH V4] RISC-V
> You mean this patch is ok?
I thought about it a bit more. From my point of view the patch is OK
for now in order to get the bug out of the way.
In the longer term I would really prefer a more "regular" solution
(i.e. via hard_regno_mode_ok) and related. I can take care of that
once I have a b
Committed, thanks Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Robin Dapp via Gcc-patches
Sent: Friday, September 15, 2023 11:44 PM
To: 钟居哲 ; Jeff Law ; kito.cheng
Cc: rdapp@gmail.com; gcc-patches ; kito.cheng
Subject: Re: [PATCH V4] RISC-V: Expand VLS mode to
kito.cheng; jeffreyalaw
Subject: Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]
> I am thinking what we are doing is something like we are allowing
> scalar mode within the vector register, so...not sure should we try to
> implement that within the mov pattern?
>
&g
I don't think it can fix the case when it is -march=rv64gc_zve32x
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-15 00:17
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]
I am thinking
To: Kito Cheng; Juzhe-Zhong
CC: rdapp.gcc; gcc-patches; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]
> I am thinking what we are doing is something like we are allowing
> scalar mode within the vector register, so...not sure should we
You mean this patch is ok?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-09-15 23:27
To: 钟居哲; kito.cheng
CC: gcc-patches; kito.cheng; rdapp.gcc
Subject: Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]
On 9/14/23 16:26, 钟居哲 wrote:
> I don't think it can fix
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