Hi!
On Mon, Jul 11, 2022 at 10:13:41AM +0800, HAO CHEN GUI wrote:
> I did a biset for the problem. After commit "commit 8d2d39587: combine: Do
> not combine
> moves from hard registers", the case fails. The root cause is it can't
> combine from the
> hard registers and has to use subreg which ca
Hi, Segher
On 8/7/2022 上午 1:31, Segher Boessenkool wrote:
>> --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
>> @@ -2,14 +2,14 @@
>> /* { dg-options "-O2" } */
>>
>> /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 14121 { target ilp32 }
Hi!
On Thu, Jul 07, 2022 at 04:30:50PM +0800, HAO CHEN GUI wrote:
> This patch modifies the combine pattern after recog fails. With a helper
It modifies combine itself, not just a pattern in the machine
description.
> - change_pseudo_and_mask, it converts a single pseudo to the pseudo AND with
Hi,
This patch modifies the combine pattern after recog fails. With a helper
- change_pseudo_and_mask, it converts a single pseudo to the pseudo AND with
a mask when the outer operator is IOR/XOR/PLUS and inner operator is ASHIFT
or AND. The conversion helps pattern to match rotate and mask insn
