Hi Xiong Hu,
On Mon, Nov 25, 2019 at 10:24:35AM +0800, luoxhu wrote:
> P9LE generated instruction is not worse than P8LE.
> mtvsrdd;xxlnot;stxv vs. not;not;std;std.
To be clear: it can have longer latency, but latency via memory is not
so critical, and this does save decode and other resources.
Hi,
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr72804-1.c
>
>> +/* store generates difference instructions as below:
>> + P9: mtvsrdd;xxlnot;stxv.
>> + P8/P7/P6 LE: not;not;std;std.
>> + P8 BE: mtvsrd;mtvsrd;xxpermdi;xxlnor;stxvd2x.
>> + P7/P6 BE: std;std;addi;lxvd2x;xxlnor;stxvd2x. */
>
Hi!
On Fri, Nov 22, 2019 at 01:26:39PM +0800, luoxhu wrote:
> Update the code as you wish, Thanks:
The point is to make this interface easy and clear to use. So please
tell me what *you* think about that, don't just do what I think may be
a good solution!
> * gcc.target/powerpc/pr72804.c:
Hi Segher,
Update the code as you wish, Thanks:
P9LE generated instruction is not worse than P8LE.
mtvsrdd;xxlnot;stxv vs. not;not;std;std.
Update the test case to fix failures.
v4:
Define and use check_effective_target_xxx etc.
power9+: power9, power10 ...
power8: power8 only.
gcc/testsuite/Cha
Hi!
On Wed, Nov 20, 2019 at 02:58:33PM +0800, luoxhu wrote:
> v3:
> Define and use check_effective_target_xxx etc.
> pre_power8: ... power6, power7.
> power8: power8 only.
> post_power8: power8, power9 ...
> post_power9: power9, power10 ...
"post_xxx" does not include "xxx", normally.
Maybe was
P9LE generated instruction is not worse than P8LE.
mtvsrdd;xxlnot;stxv vs. not;not;std;std.
Update the test case to fix failures.
v3:
Define and use check_effective_target_xxx etc.
pre_power8: ... power6, power7.
power8: power8 only.
post_power8: power8, power9 ...
post_power9: power9, power10 ...
