Hi Kyrill,
Thanks your reply.
On 2018/9/26 19:20, Kyrill Tkachov wrote:
> Hi Shaokun,
>
> On 25/09/18 14:40, Zhangshaokun wrote:
>> Hi ARM maintainers,
>>
>> Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC?
>> I saw it has been supported in linux mainline(on Mar 7),
>> Patch link:
>> http
Hi Shaokun,
On 25/09/18 14:40, Zhangshaokun wrote:
Hi ARM maintainers,
Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC?
I saw it has been supported in linux mainline(on Mar 7),
Patch link:
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/565090.html
Kernel link:
https://g
Hi ARM maintainers,
Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC?
I saw it has been supported in linux mainline(on Mar 7),
Patch link:
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/565090.html
Kernel link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.
Hi Kyrill,
On 2018/9/21 20:25, Kyrill Tkachov wrote:
> Hi Shaokun,
>
> On 20/09/18 15:54, Zhangshaokun wrote:
>> Hi James,
>>
>> On 2018/9/20 22:22, James Greenhalgh wrote:
>>> On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote:
This patch adds HiSilicon's an mcpu: tsv110, which s
Hi Shaokun,
On 20/09/18 15:54, Zhangshaokun wrote:
Hi James,
On 2018/9/20 22:22, James Greenhalgh wrote:
On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote:
This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A.
It has been tested on aarch64 and no regressions from this
Hi James,
On 2018/9/20 22:22, James Greenhalgh wrote:
> On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote:
>> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A.
>> It has been tested on aarch64 and no regressions from this patch.
>
> This patch is OK for Trunk.
>
> Do
On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote:
> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A.
> It has been tested on aarch64 and no regressions from this patch.
This patch is OK for Trunk.
Do you need someone to commit it on your behalf?
Thanks,
James
>
>
This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A.
It has been tested on aarch64 and no regressions from this patch.
---
gcc/ChangeLog| 9 +++
gcc/config/aarch64/aarch64-cores.def | 3 +
gcc/config/aarch64/aarch64-cost-tables.h | 104 +++