On Mon, Apr 14, 2014 at 6:13 PM, Terry Guo wrote:
> On Thu, Apr 3, 2014 at 10:11 PM, Eric Botcazou wrote:
>>> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
>>> (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4) to zero
>>> during the fwprop1 pass, cons
On Thu, Apr 3, 2014 at 10:11 PM, Eric Botcazou wrote:
>> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
>> (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4) to zero
>> during the fwprop1 pass, considering the fact that the high 32-bit part of
>> (a & 0x
> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
> (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4) to zero
> during the fwprop1 pass, considering the fact that the high 32-bit part of
> (a & 0x) is zero. This leads to some unnecessary multiplic
Hello Eric,
Would you please review my patch at
http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01582.html? Thanks.
BR,
Terry
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Friday, March 28, 2014 3:48 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch]Simplify SUBREG with operand whose target bits are cleared
Hi there,
When compile below case for ARM Thumb-2 target:
long long int
test (unsigned long long int a, unsigned int b)
{
return (a & 0x) * b;
}
I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
(and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4)
