Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-15 Thread Eric Botcazou
> > OK, revised patch attached. I have manually verified that it yields the > > expected result for an array of long doubles on 64-bit SPARC. > > > > > > 2019-02-12 Eric Botcazou > > > > * asan.c (asan_expand_mark_ifn): Take into account the alignment of > > the object to pick the

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-12 Thread Jakub Jelinek
On Tue, Feb 12, 2019 at 12:41:47PM +0100, Eric Botcazou wrote: > > Ok, stand corrected on that, 128-bit indeed, but even that is nothing not > > really used. > > The irony is that I'm doing this for 32-bit SPARC (we cannot get ASAN to work > in 64-bit mode for the time being) and the maximum

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-12 Thread Eric Botcazou
> Ok, stand corrected on that, 128-bit indeed, but even that is nothing not > really used. The irony is that I'm doing this for 32-bit SPARC (we cannot get ASAN to work in 64-bit mode for the time being) and the maximum alignment on 32-bit SPARC is 64-bit (even long doubles) so this will be

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-11 Thread Jakub Jelinek
On Mon, Feb 11, 2019 at 01:31:24PM +0100, Eric Botcazou wrote: > > No. 64-bit aligned offsets too. If you know 64-bit alignment of base_addr, > > you can use size 2 stores (though not size 4 stores) on the > > !STRICT_ALIGNMENT targets. And that is something still pretty common. > > But we're

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-11 Thread Eric Botcazou
> No. 64-bit aligned offsets too. If you know 64-bit alignment of base_addr, > you can use size 2 stores (though not size 4 stores) on the > !STRICT_ALIGNMENT targets. And that is something still pretty common. But we're talking about STRICT_ALIGNMENT targets here: an array of 2 doubles at

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-11 Thread Jakub Jelinek
On Mon, Feb 11, 2019 at 12:31:43PM +0100, Eric Botcazou wrote: > > So, wouldn't it be better to check for STRICT_ALIGNMENT > > get_pointer_alignment (base_addr) and do this only if that alignment > > (shifted right by ASAN_SHADOW_SHIFT) is not sufficient and e.g. if we would > > know that the

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-11 Thread Eric Botcazou
> So, wouldn't it be better to check for STRICT_ALIGNMENT > get_pointer_alignment (base_addr) and do this only if that alignment > (shifted right by ASAN_SHADOW_SHIFT) is not sufficient and e.g. if we would > know that the shadow is at least 2 byte aligned but not 4 byte aligned, use > size = 2

Re: [patch] Disable store merging in asan_expand_mark_ifn

2019-02-11 Thread Jakub Jelinek
On Mon, Feb 11, 2019 at 11:03:41AM +0100, Eric Botcazou wrote: > asan_expand_mark_ifn does manual store merging but doesn't take into account > the alignment, so this can break on strict-alignment platforms. > > Tested on SPARC/Solaris 11, where this fixes this regression: > > FAIL:

[patch] Disable store merging in asan_expand_mark_ifn

2019-02-11 Thread Eric Botcazou
Hi, asan_expand_mark_ifn does manual store merging but doesn't take into account the alignment, so this can break on strict-alignment platforms. Tested on SPARC/Solaris 11, where this fixes this regression: FAIL: gcc.dg/asan/use-after-scope-5.c -O0 output pattern test FAIL: