On 4/6/23 04:15, Eric Botcazou wrote:
Originally I didn't really see this as an operation. But the more and
more I ponder it feels like it's an operation and thus should be subject
to WORD_REGISTER_OPERATIONS.
While it's not really binding on RTL semantics, if we look at how some
On 4/6/23 03:37, Li, Pan2 wrote:
Yes, RISC-V riscv.h defined the WORD_REGISTER_OPERATIONS to be 1, while
aarch64.h defined it as 0, with below comments. No idea this can fit RISC-V or
not.
I don't see any fundamental reason why it won't work. Most of the
expansion code already has code
On 4/6/23 03:31, Richard Sandiford wrote:
Jeff Law writes:
On 4/5/23 10:48, Jakub Jelinek wrote:
On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote:
It is true that an instruction like
(insn 8 7 9 2 (set (reg:HI 141)
(subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181
> Originally I didn't really see this as an operation. But the more and
> more I ponder it feels like it's an operation and thus should be subject
> to WORD_REGISTER_OPERATIONS.
>
> While it's not really binding on RTL semantics, if we look at how some
> architectures implement reg->reg copies,
, April 6, 2023 5:31 PM
To: Jeff Law
Cc: Jakub Jelinek ; Richard Biener ; Eric
Botcazou ; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] dse: Handle SUBREGs of word REGs differently for
WORD_REGISTER_OPERATIONS targets [PR109040]
Jeff Law writes:
> On 4/5/23 10:48, Jakub Jelinek wrote:
>&g
Jeff Law writes:
> On 4/5/23 10:48, Jakub Jelinek wrote:
>> On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote:
It is true that an instruction like
(insn 8 7 9 2 (set (reg:HI 141)
(subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_internal}
(nil))
On 4/5/23 10:48, Jakub Jelinek wrote:
On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote:
It is true that an instruction like
(insn 8 7 9 2 (set (reg:HI 141)
(subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_internal}
(nil))
can appear in the IL on
On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote:
> > It is true that an instruction like
> > (insn 8 7 9 2 (set (reg:HI 141)
> > (subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_internal}
> > (nil))
> > can appear in the IL on WORD_REGISTER_OPERATIONS target, but I
On 4/5/23 08:51, Jakub Jelinek wrote:
On Wed, Apr 05, 2023 at 07:14:23AM -0600, Jeff Law wrote:
The following testcase is miscompiled on riscv since the addition
of *mvconst_internal define_insn_and_split.
I believe the bug is in DSE. We have:
(insn 36 35 39 2 (set (mem/c:SI (plus:SI
On Wed, Apr 05, 2023 at 07:14:23AM -0600, Jeff Law wrote:
> > The following testcase is miscompiled on riscv since the addition
> > of *mvconst_internal define_insn_and_split.
> > I believe the bug is in DSE. We have:
> > (insn 36 35 39 2 (set (mem/c:SI (plus:SI (reg/f:SI 65 frame)
> >
On 4/5/23 03:16, Jakub Jelinek wrote:
Hi!
The following testcase is miscompiled on riscv since the addition
of *mvconst_internal define_insn_and_split.
I believe the bug is in DSE. We have:
(insn 36 35 39 2 (set (mem/c:SI (plus:SI (reg/f:SI 65 frame)
(const_int -64
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