On Thu, Jul 14, 2022 at 7:32 AM Roger Sayle wrote:
>
>
> On Mon, Jul 11, 2022, H.J. Lu wrote:
> > On Sun, Jul 10, 2022 at 2:38 PM Roger Sayle
> > wrote:
> > > Hi HJ,
> > >
> > > I believe this should now be handled by the post-reload (CSE) pass.
> > > Consider the simple test case:
> > >
> > >
On Mon, Jul 11, 2022, H.J. Lu wrote:
> On Sun, Jul 10, 2022 at 2:38 PM Roger Sayle
> wrote:
> > Hi HJ,
> >
> > I believe this should now be handled by the post-reload (CSE) pass.
> > Consider the simple test case:
> >
> > __int128 a, b, c;
> > void foo()
> > {
> > a = 0;
> > b = 0;
> > c
On Sun, Jul 10, 2022 at 8:36 PM Roger Sayle wrote:
>
>
> Hi Uros,
> Yes, I agree. I think it makes sense to have a single STV pass (after
> combine and before reload). Let's hear what HJ thinks, but I'm
> happy to investigate a follow-up patch that unifies the STV passes.
> But it'll be easier
On Sun, Jul 10, 2022 at 2:38 PM Roger Sayle wrote:
>
>
> Hi HJ,
>
> I believe this should now be handled by the post-reload (CSE) pass.
> Consider the simple test case:
>
> __int128 a, b, c;
> void foo()
> {
> a = 0;
> b = 0;
> c = 0;
> }
>
> Without any STV, i.e. -O2 -msse4 -mno-stv, GCC
Hi HJ,
I believe this should now be handled by the post-reload (CSE) pass.
Consider the simple test case:
__int128 a, b, c;
void foo()
{
a = 0;
b = 0;
c = 0;
}
Without any STV, i.e. -O2 -msse4 -mno-stv, GCC get TI mode writes:
movq$0, a(%rip)
movq$0, a+8(%rip)
On Sun, Jul 10, 2022 at 11:36 AM Roger Sayle wrote:
>
>
> Hi Uros,
> Yes, I agree. I think it makes sense to have a single STV pass (after
> combine and before reload). Let's hear what HJ thinks, but I'm
> happy to investigate a follow-up patch that unifies the STV passes.
> But it'll be easier
Hi Uros,
Yes, I agree. I think it makes sense to have a single STV pass (after
combine and before reload). Let's hear what HJ thinks, but I'm
happy to investigate a follow-up patch that unifies the STV passes.
But it'll be easier to confirm there are no "code generation" changes
if those
On Sat, Jul 9, 2022 at 2:17 PM Roger Sayle wrote:
>
>
> This patch upgrades x86_64's scalar-to-vector (STV) pass to more
> aggressively transform 128-bit scalar TImode operations into vector
> V1TImode operations performed on SSE registers. TImode functionality
> already exists in STV, but only
