Since vms pattern has one more tail policy + avl_type operand,
wheras pred_mov (vmset.m/vmclr.m) only has avl_type operand.
GCC recognize (lt:(reg v) (reg v)) and lower it into (const_vector:0),
then map into pred_mov pattern (when both pred_mov and vms pattern has
tail policy + avl_type operand).
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be
written into the commit log.
> gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_pred_op):
>* config/riscv/riscv-vector-builtins-bases.cc:
>* config/riscv/vector.
: Allow VMS{Compare} (V1, V1) shortcut
optimization
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be written into
the commit log.
> gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_pred_op):
>* config/r
Cc: gcc-patches ; Kito.cheng ;
Wang, Yanzhang
Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
optimization
Sure thing.
For Changlog, I consider it was generated automatically in previous. LOL.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, April 19
s' ; 'Kito.cheng'
; Wang, Yanzhang
Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
optimization
Update the Patch v2 for more detail information for clarification. Please help
to review continuously.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
;
>
> Cc: 'gcc-patches' ; 'Kito.cheng'
> ; Wang, Yanzhang
> Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Update the Patch v2 for more detail information for clarification. Please
> help to review continuously
e.zh...@rivai.ai'
>
> Cc: 'gcc-patches' ; 'Kito.cheng'
> ; Wang, Yanzhang
> Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Update the Patch v2 for more detail information for clarification. Please
> h
--Original Message-
> From: Kito Cheng
> Sent: Friday, April 21, 2023 6:17 PM
> To: Li, Pan2
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
> ; Wang, Yanzhang
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> I got a bunch
PM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
; Wang, Yanzhang
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
optimization
Hi Pan:
One idea come to my mind, maybe we should add a new define_insn_and_split
pattern instead of change @pred_mov
On Fri, A
---
> From: Kito Cheng
> Sent: Friday, April 21, 2023 9:02 PM
> To: Li, Pan2
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
> ; Wang, Yanzhang
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Hi Pan:
>
> One ide
g the decision? Thanks in advance!
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, April 25, 2023 9:08 PM
To: Li, Pan2 ; Jeff Law
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
; Wang, Yanzhang
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
optimiz
: Li, Pan2 ; Jeff Law
> Cc: juzhe.zh...@rivai.ai; gcc-patches ;
> Kito.cheng ; Wang, Yanzhang <
> yanzhang.w...@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Second thought on this, we should just add define_split rather t
h...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; gcc-patches
> mailto:gcc-patches@gcc.gnu.org>>;
> Kito.cheng mailto:kito.ch...@sifive.com>>; Wang,
> Yanzhang
> mailto:yanzhang.w...@intel.com>>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
&
.com>>; Jeff Law
mailto:jeffreya...@gmail.com>>;
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; gcc-patches
mailto:gcc-patches@gcc.gnu.org>>; Wang, Yanzhang
mailto:yanzhang.w...@intel.com>>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
opt
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