Dan McMahill wrote:
Andy Peters wrote:
On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote:
On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote:
No back-annotation.
This is VERY important to me. As part of general cleanup after
finishing a layout, I renumber all of the
Dan McMahill wrote:
Dan McMahill wrote:
Andy Peters wrote:
On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote:
On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote:
No back-annotation.
This is VERY important to me. As part of general cleanup after
finishing a layout,
Hello,
I'm at the stage of processing my design through gnetlist so I can track down
all the errors.
I'm having a little trouble with the output generated by a call like:
gnetlist -v -g drc2 pedio_5i20Aconn.sch pedio_5i20Bconn.sch ... (lots
more .sch files) ... -o drc_output.txt
On 2/26/07, Seb James [EMAIL PROTECTED] wrote:
Checking slots...
ERROR: Multislotted reference U? has no slot attribute defined.
It would be very useful if the schematic on which the U? element appears was
printed. The program where this should happen is get-drc2.scm. Having only
programmed a
Seb James wrote:
I tried that, but it seems that the component doesn't have an explicit refdes
of U?. I suppose that somewhere there is a component which is missing the
refdes altogether.
If you search all your output files, ( -o drc_output.txt drc_stdout.txt
2drc_stderr.txt), for the same
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
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Hi,
the DRC tells me Line with insufficient clearance inside polygon. If
I do Ctrl+R on the line in question, the clearance is correctly shown as
5.91mils (actually 0.15mm). 0.15mm is also my configured DRC clearance.
Might that just be a rounding error which I can ignore?
regards,
David
--
Hi again,
I defined a new symbol, for the Mesa Electronics 7I33 daughter board.
This has 104 pins, of which about half connect to ground.
The start of the symbol file is appended to the end of this email, and I
attached the complete symbol file.
If you look at the first 15 lines or so, you'll
On Monday 26 February 2007 16:06, Seb James wrote:
Hi again,
I defined a new symbol, for the Mesa Electronics 7I33 daughter board.
This has 104 pins, of which about half connect to ground.
The start of the symbol file is appended to the end of this email, and I
attached the complete symbol
DJ == DJ Delorie [EMAIL PROTECTED] writes:
the DRC tells me Line with insufficient clearance inside polygon.
If I do Ctrl+R on the line in question, the clearance is correctly
shown as 5.91mils (actually 0.15mm). 0.15mm is also my configured
DRC clearance.
Look for tiny traces under the
DJ == DJ Delorie [EMAIL PROTECTED] writes:
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
Here is a simplified file that only contains the problematic footprint.
Quite possibly this is just a problem with the footprint? After
Hi,
just another strange DRC error.
This is caused by the oldlib-generated footprint SMT_DIODE 15 8:
Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09
min drill 1.00, min annular ring 15.75
Element Z50 has 5 silk lines which are too thin
near location
About dinotrace
How
'bout Stuart's big build CD?
Good idea. I just added it to the ToDo list.
Stuart
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Hi Dan and all,
On Monday 26 February 2007 17:20, Stephen Williams wrote:
Is it wrapped up into any Linux packages? Can you convince Werner
to include it in his set of tools that he packages for SuSE? How
'bout Stuart's big build CD?
Really, in the Linux world, dinotrace seems to be a well
Al Hooton wrote:
This is on a vanilla install of Mandriva 2007.0. I have looked through
the list archives, the INSTALL information and googled around, but I'm
stuck. Hopefully somebody here has the answer as to why the installer
just suddenly gives up near the beginning of things.
Just showed up today...
http://www.delorie.com/house/furnace/pcb2/
First observations: pcb-pool's drills (m32c board) were off center a
bit, coming close to touching the edges of the copper. Advanced
Circuit's drills seem to be much more accurately aligned.
I put 1 2 3 4 on each layer, it
DJ Delorie wrote:
Just showed up today...
The teardrops look nice, DJ.
What are the 3 long pads that appear next to some of the 20 pin and 32
pin footprints (on the top)?
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The teardrops look nice, DJ.
Thanks! I've had traces detach from pins during rework, I'm hoping
that the teardrops avoid the hard inside corners that sometimes lead
to failure.
Plus they're pretty :-)
What are the 3 long pads that appear next to some of the 20 pin and
32 pin footprints (on
I am putting together a master parts list table for my component
database. I am trying to determine a good format for component part
numbers. Are there any industry standards for this type of information?
IPC documentation?
I was thinking of starting with some of the IPC-7351 component
category
On Mon, 26 Feb 2007 16:06:57 +
Seb James [EMAIL PROTECTED] wrote:
Problem 2
--
I am placing this symbol in a design which is split into two regions, with
opto-isolators connecting them. This means I have two ground nets, and I also
have two 5V nets.
Instead of using the
Gah! Attaching .sym's help.
-Lares
ATMega640-1280-2560_ADC.sym
Description: Binary data
ATMega640-1280-2560_IO1.sym
Description: Binary data
ATMega640-1280-2560_IO2.sym
Description: Binary data
ATMega640-1280-2560_pwr.sym
Description: Binary data
pgp0b6ysaTX1h.pgp
Description: PGP
David Kuehling wrote:
DJ == DJ Delorie [EMAIL PROTECTED] writes:
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
Here is a simplified file that only contains the problematic footprint.
Quite possibly this is just a
David Kuehling wrote:
Hi,
just another strange DRC error.
This is caused by the oldlib-generated footprint SMT_DIODE 15 8:
Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09
min drill 1.00, min annular ring 15.75
Element Z50 has 5 silk lines which are too thin
near
Marc Moreau wrote:
On Mon, 26 Feb 2007 16:06:57 +
Seb James [EMAIL PROTECTED] wrote:
Instead of using the nets GND and +5V, I have gnd_left and gnd_right and
+5v_left and +5v_right.
Can I redefine the nets for those pins after I
placed the symbol in my schematic?
Looking at your
OK, I'm an idiot. How do I create a local (as in local to my
design directory) library of PCB footprints? All the documentation
I see suggests that it will automatically search in the packages
directory in the current workig directory. No?!
--
Steve WilliamsThe woods are lovely,
OK, I'm an idiot. How do I create a local (as in local to my design
directory) library of PCB footprints? All the documentation I see
suggests that it will automatically search in the packages
directory in the current workig directory. No?!
Note that a local directory *overrides* the global
On Mon, Feb 26, 2007 at 07:59:02PM -0500, DJ Delorie wrote:
Note that a local directory *overrides* the global one, as pcb only
supports one library at a time (er, one each of m4 and newlib).
Agh can I add that as a wart? I don't remember this happening
to me, but it might explain why
Agh can I add that as a wart?
Yup :-)
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DJ Delorie wrote:
OK, I'm an idiot. How do I create a local (as in local to my design
directory) library of PCB footprints? All the documentation I see
suggests that it will automatically search in the packages
directory in the current workig directory. No?!
Note that a local directory
I'm puzzled by this response. Under File-Preferences in the
Library tab there is an entry box for Element directories that
asks for a colon separated list of directories. Where does this
list get stored?
These are the times I like it when I'm wrong. Both gtk and lesstif
allow
DJ Delorie wrote:
OK, I'm an idiot. How do I create a local (as in local to my design
directory) library of PCB footprints? All the documentation I see
suggests that it will automatically search in the packages
directory in the current workig directory. No?!
When you say it will automatically
Dan McMahill wrote:
David Kuehling wrote:
DJ == DJ Delorie [EMAIL PROTECTED] writes:
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
Here is a simplified file that only contains the problematic footprint.
Quite
DJ Delorie wrote:
I'm puzzled by this response. Under File-Preferences in the
Library tab there is an entry box for Element directories that
asks for a colon separated list of directories. Where does this
list get stored?
These are the times I like it when I'm wrong. Both gtk and lesstif
[snip]
OK, wart alert. I go into preferences and I expect to see the
[snip]
I'll file bug reports for these.
Thank you Steve. Not speaking for the PCB developers, but I'm sure they
appreciate the bug reports; I know I do.
Just a reminder that there are really only three ways to get
Thank you Steve. Not speaking for the PCB developers, but I'm sure they
appreciate the bug reports; I know I do.
We appreciate all the feedback, with the understanding that we can
only get to a tiny percentage of it at a time, as there's only a few
of us, and we only do this as a hobby.
DJ Delorie wrote:
Thank you Steve. Not speaking for the PCB developers, but I'm sure they
appreciate the bug reports; I know I do.
We appreciate all the feedback, with the understanding that we can
only get to a tiny percentage of it at a time, as there's only a few
of us, and we only do
I'll tell you what. I'll pay you to fix your bugs if you pay me
to fix mine. Deal? :-)
Fixing my own bugs is usually at the top of *my* todo list. But my
comment...
We appreciate all the feedback,
... applies to more than just bug fixes. We also appreciate feedback
about design choices,
Stephen Williams wrote:
DJ Delorie wrote:
Thank you Steve. Not speaking for the PCB developers, but I'm sure they
appreciate the bug reports; I know I do.
We appreciate all the feedback, with the understanding that we can
only get to a tiny percentage of it at a time, as there's only a few
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