On Sun, 18 Mar 2007, al davis wrote:
>> * Finally, how should PCB behave with a hierarchical
>> schematic?
>
>Right click on a symbol, select "go inside", and another drawing
>opens up showing what's inside. gschem also should act this
>way.
I like this idea very much. In case of PCB it also
On Saturday 17 March 2007 00:13, John Griessen wrote:
> David Baird wrote: (about data tie ins to higher
> abstractions than "just boards")jg I've been thinking (maybe
> just dreaming?) about an extensible system which allows the
> representation of information which has not yet even been
> en
My imediate use for recessing has to do with ridged flex riged boards.
In one example we have a circuit board that has for example a ridged
section on the right that has a connector, this section has to have one
level of thickness. connected to this ridged is a section of flex, on
the other side of
Wow, thanks for the quick responses !
> Does iverilog support SDF backannotation? The SDF has the delay
> information.
Ah ! Now you mention it, I remember removing a $sdf_annotate line
from the generated verilog file. It was causing an error with vvp,
so I just removed the offending line and q
> One practical solution for very small parts is to hid the refdes on the
> board but make a large assembly drawing that has them.
That's almost what I did. I make the refdes's as big as the parts,
right on top of them, and printed them out as an assembly drawing. I
just didn't put them on a si
One practical solution for very small parts is to hid the refdes on the
board but make a large assembly drawing that has them.
Steve Meier
DJ Delorie wrote:
>> S2/S2/L1 S2/S2/C1 and S2/S2/U1
>>
>> is the RenumberBlock funtion capable of this?
>>
>
> It currently pulls the last string of dig
Andy Peters wrote:
the
static timing analyzer (using your timing constraints) tells you if
you've met timing. If both are good, there's no need to run a post-fit
simulation.
Dr. Deming told us that the Asian focus on direction of most closely
approaching perfection
is a better goal than arbit
On Mar 17, 2007, at 3:15 PM, CSB wrote:
Hi all,
I am trying to use Iverilog along with xilinx's SIMPRIMS. Well,
I managed, but I am getting strange results with simulations.
I'll try to explain how I'm doing this (I'm new to CPLDs, Verilog
and Icarus...)
First, I generate the post-fit verilog
Hi all,
I am trying to use Iverilog along with xilinx's SIMPRIMS. Well,
I managed, but I am getting strange results with simulations.
I'll try to explain how I'm doing this (I'm new to CPLDs, Verilog
and Icarus...)
First, I generate the post-fit verilog module from Xilinx ISE
project navigator.
If you edit the .pcb file and remove all the Rats[] entries (they're
all at the end) it will at least load. However, all the layer
information is missing, so you'll have to re-add all the layers and
redefine the layer groups.
Do you have a save file in /tmp, or in the same directory as the
origi
Hi all!
I tried out the gEDA package and I am very impressed! My thanks to all
who contributed to this project!
I created a layout in pcb and just needed the last finish before the
board was done. Unfortunately I marked two rats nets together with
my component which I wanted to delete. When I hit
http://geda.seul.org/wiki/geda:design_flow_and_hierarchy_roadmap
Has current comments pro and con and feasibility.
I paraphrased and edited. Please tell me if it was too much
without YELLING. :-)
John G
___
geda-user mailing list
geda-user@moria.s
DJ Delorie <[EMAIL PROTECTED]> wrote:
>
>> While I am at it. PCB should be able to do hidden vias, buried vias
>> and micro vias...
>
> If we can get the "layer types" project done (this is listed as the
> non-copper layers project in SoC), we'll be able to have a concept of
> a "layer stack" (un
13 matches
Mail list logo
